Abstract
This paper deals with the hardware implementation of a set of basic algorithms used by the HERMES lower-level nodes for vision preprocessing. HERMES is a multilevel, neuromorphic vision net. It consists of ( N 2 i ) × ( N 2 i ) nodes in a 2-D array configuration, where N × N represents the image size, and “i” is a resolution parameter. The HERMES net receives images directly fom the environment by using a 2-D photoarray, and processes them in a parallel hierarchical (bottom-up and top-down) asynchronous manner. Each system node is a neuromorphic net making the overall HERMES function quickly and efficiently. The nodes are also capable of learning a variety of patterns, and adjust themselves easily to variations of the input images. Since the lower-level nodes comprise more than 75% of the HERMES nodes, the VLSI implementation of the lower-level nodes plays a significant role in the VLSI realization of HERMES.
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