Hardware acceleration of homogeneous and heterogeneous ensemble classifiers

Abstract

In this paper a universal reconfigurable computing architecture for hardware implementation of homogeneous and heterogeneous ensemble classifiers composed from decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs) is proposed. The following types of ensemble classifiers have been implemented in FPGA using proposed architecture: homogeneous ensemble classifiers composed from two versions of DT (Functional DT and Axis-Parallel DT), two versions of SVM (with polynomial and radial kernel) and two versions of ANN (Multilayer Perceptron ANN and Radial Basis ANN) machine learning predictive models, as well as a number of types of heterogeneous ensemble classifiers composed of a mixtures of DTs, SVMs and ANNs. Comparison of the FPGA implementation of REC architecture with standard WEKA software implementation suggests that proposed hardware architecture offers substantial speed-ups for all types of considered machine learning ensemble classifiers, ranging from 102 to 105 times.