Hard real-time bus architecture and arbitration algorithm based on AMBA

Abstract

Real-time processors are growly used in embedded applications. Considering that the time cost in data transfer among devices is much more than the time used for computation and operation, it's important to design a high-speed real-time bus structure in real-time systems. This paper offers a deep investigation to the characteristics of real-time systems as well as the basic structure of real-time processors and real-time buses. We designed a high-speed and time-predictable bus architecture called RTBus, where high-performance AXI protocol is employed. To accurately calculate the bus access time for master devices, a two-level real-time bus arbitration algorithm, which adopts the warning-line judgment mechanism and simulated annealing algorithm, is proposed for the operation of the RTBus. Finally, it is proved that RTBus provides a good solution to the conflicts when sharing resources in real-time processors.