Guideline to avoid cracking in 3D TSV design

Abstract

Three dimensional through-silicon via (3D TSV) technology emerges due to the requirement of high performance, low cost and small form factor in the three dimensional packaging technology. The typical TSV structure is a thin silicon wafer drilled with through hole, the inside wall of the hole is plated with dielectric SiO 2 and diffusion barrier such as Ta, and then the hole is filled by Cu or W as the conductor. During fabrication, testing and service, the packages with TSV structures usually undergo temperature excursion. When the operation temperature is higher than stress-free temperature, the expansion of metal via will induces tensile stresses in circumferential direction in silicon interposer due to the mismatch of coefficient of thermal expansion. The tensile stress could drive the microcracks within the SiO 2 and silicon to initiate and finally break the silicon interposer by radial cracking. In the current paper, a design guideline is established based on fracture mechanics to avoid such failure, including the parameters such as via radius, flaw size, Young's modulus, coefficient of thermal expansion, and fracture toughness. The explicit expression in mathematical form makes such a guideline easily implemented in 3D TSV design.