General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters

Abstract

Energy loss due to top/bottom plate parasitic capacitances is one of the factors determining the efficiency of integrated switched capacitor DC/DC converters. This loss is particularly significant when MOS gate or deep trench capacitors are used. We propose a technique for top/bottom-plate charge recycling that can be applied with low overhead independently of the converter architecture. Two examples of application of the technique are presented. First, it is shown how the technique can be applied to any converter by transforming it to an interleaved implementation. This approach is demonstrated in a series-parallel 1/3 down converter achieving a maximum load power of 240 μW. Simulation results show an improvement of 7% in the efficiency by decreasing the top/bottom-plate parasitic capacitance losses by 52%. The second example considers an architecture where the proposed technique can be directly applied without additional transformations of the converter implementation. It is a ring modular architecture converter, which was fabricated in a 130 nm CMOS process. An efficiency improvement of up to 4% was achieved in measurements by reducing the top/bottom plate losses by 70%, thus reaching an outstanding efficiency of 80.6% at a conversion ratio of 2/3 and a maximum load power of 2.2 mW.