Abstract

The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

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