Gate Level Information Flow analysis for multi-valued logic system

Abstract

As the scale of integrated circuits continuously increasing, guaranteeing intensity of testing and coverage rate of verification in the design phase absolutely is becoming severe challenges. As a solution, Gate Level Information Flow Tracking (GLIFT) method is able to precisely measure all the logical information flows in the underlying hardware to prevent information leakage resulting from these harmful flows of information. However, preliminary research work for GLIFT mainly focused on the basic theories as well as the generation algorithms, which only can track logic formalization under the Boolean logic system. These approaches ignored that digital circuits are typically described by multi-valued logic during hardware design and verification. To address that issue, we present to expand the GLIFT method for multi-valued logic system. In this paper, the label propagation rule set is respectively derived for four-valued and nine-valued logic systems by extending the label propagation set for Boolean logic. Moreover, in order to support the characteristics of multi-valued logic in label propagation, the formal descriptions of GLIFT logic for primitive gates are improved in computing hardware as well. The experimental results demonstrate that the extended method is consistent with the label propagation rule of the multi-valued logic system.