Gate Leakage Current Effects on the Linearity of 28GHz CMOS SOI Power Amplifiers

Abstract

In order to improve the linearity of power amplifiers (PAs), it is desirable to design for a “sweet spot” in the $3 ^{rd}$ order intermodulation distortion at a critical power, at which the distortion is significantly decreased. The appearance of “sweet spots” often accompanies the presence of slight amounts of gain expansion that counter the gain compression which results from PA output saturation, and can be influenced by power-dependent input biasing. This paper illustrates that in mm-wave CMOS SOI FET PAs, gain expansion and sweet spots are produced at appropriate gate bias conditions, and are influenced by the variation of gate bias voltage with output power. The gate bias change is affected by small gate leakage currents together with large value resistors in the input bias network. Experimental results are presented using 2-stack 28GHz power amplifiers implemented with 45nm CMOS SOI which achieve peak output power of 19dBm and 43% PAE, and can attain high linearity without DPD. As input power is increased, gate leakage current varies by up to 3-5uA. With external gate bias resistors of order $10-50K \Omega$, gate bias voltages can increase by 50-100mV, which impacts the AM-AM curve affecting gain expansion. Two tone measurements show the formation of sweet spots at which IM3 decreases on order of 5-10dB at output power levels of order of 5dB backed off from P1dB. The extent of the sweet spot is influenced by the external gate bias resistor.