Abstract

This paper presents a simulation study of the gate current through stacked dielectrics of interest for advanced nonvolatile memory (NVM) cells possibly employing high-k insulators to engineer the tunnel barrier. Program, retention and read disturb conditions are analyzed. The impact of modeling approximations on the predictions of the programming gate current in Fowler-Nordheim (FN) and channel hot electron (CHE) injection regimes is critically discussed. Comparison with a reference SiO/sub 2/ device allows us to identify some of the possible advantages and limitations of these stacks for future NVM.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.