GaN Nano Air Channel Diodes with Ultralow Turn-On Voltages for NAND Logic Circuits.

Over the past few years tremendous progress has been made on the process, application, device physics and compact modeling of nanowire MOSFETs. We would like to review the above aspects of silicon-based nanowire, focusing on its crucial compact models and the circuit performance demonstration based on our group research work and understanding on nanowire MOSFET progress. Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. Both the top-down (Singh et al., 2008) and bottom-up (Lu & Lieber, 2006) approaches are widely studied to prepare ultra small nanowire. With bottom-up method, nanowires are generally synthesized by using metal nanoclusters as catalysts via a vapor-liquid-solid process (Lu & Lieber, 2006). After growth nanowires are transferred to silicon substrate to form FET structure. With top-down technique there are various fabrication approaches, such as hard mask trimming, etching in H2 ambient and stress limited oxidation (Singh et al., 2008). 5-nm gate length device has been demonstrated (Liow et al., 2008). Nanowire MOSFETs prepared with both methods find application in logic circuits (Singh et al., 2008), memory (Singh et al., 2008) and sensors (Stern et al., 2008). Due to the quantum confinement in cross section of nanowire MOSFETs, especially of nanowires with diameter smaller than 15nm, electron mobility behaves differently from its bulk counterpart. Phonon-limited electron mobility decreases with reducing the wire size (Kotlyar et al., 2004) while total electron mobility is enhanced due to volume inversion at high transverse field (Jin et al., 2007). Although whether or not ballistic transport can occur in the silicon nanowire MOSFETs with ultrasmall channel length is disputable (Ferry et al., 2008), it deserves our attention. In the ballistic transport regime, carrier scattering in the device channel is totally suppressed. The study of ballistic transport in nanowire MOSFETs provides the upper limit to their performances. Under extreme scaling of nanowire MOSFETs, the atoms in nanowire cross section are countable. It is believed that the change in bandstructure of one dimensional nanowire influences the device performances (Neophytou et al., 2008). The above mentioned phenomenon are studied and simulated with various numerical approaches and also need to be accounted for in the advanced compact models.

Single Si-substituted monolayer Si-doped graphene (Si:Gr) with one carbon atom in hexagon of graphene substituted by Si atom, studied by density functional theory (DFT) calculation has a range of structural and electronic features. The Si:Gr demonstrates absorbed-atom geometric structure, silicon-carbon dominated energy bands, atom-orbital projected density of states and charge concentration in space. These critical characteristics generate distinct physical and electrical properties of the unique material Si:Gr permitting it to be utilized as semiconductor material. Due to very high carrier mobility and saturation velocity, graphene devices are very useful in radio frequency (RF) applications. Recent studies suggest that utilizing bare silicon as a supporting substrate without an insulating layer under the channel region in conventional graphene-field effect transistor (GFET) can result in high output resistance and voltage gain, which provides higher cut-off frequency comparing with conventional GFET. In this work, an N-channel GFET with printed channel length of 50nm has been designed with Si:Gr as channel material where the Si:Gr is deposited on lightly doped p-type silicon substrate eliminating the insulator layer in between. For optimum RF performance bottom gate with SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as back gate dielectric has been utilized. The device has provided a maximum cut-off frequency of 788GHz and Ion/Ioff ratio of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.7\times 10^{6}$</tex> (bottom gate, metallic contact) proposing a novel device for RF and logic circuit applications.

Ambipolar organic electrochemical transistors (OECTs) with a single organic mixed ionic‐electronic conductor (OMIEC) have unique advantages by reducing fabrication complexity and cost in complementary logic circuit and bioelectronic applications. However, the design and synthesis of high‐performance ambipolar OMIECs for efficient transport and coupling both cation/anion and electron/hole remain challenging. Herein, a donor–acceptor (D–A)‐typed ambipolar OMIEC polymer (DHF‐gTT) is presented, whose superior ambipolarity stems from the concurrent oligoethyleneglycol‐functionalized D/A units that facilitates cation/anion injection and transport. Additionally, the fluorination of acceptor unit improves both hole/electron transports due to the fully‐locked backbone and promotes electron injection by down‐shifting molecular energy levels. Consequently, DHF‐gTT‐based OECTs achieve balanced figure‐of‐merit (µC*) for both p‐type and n‐type operations (12.4–14.6 F cm−1 V−1 s−1), setting new benchmarks for ambipolar OECTs, in terms of n‐type µC* and electron/hole mobilities. Such ambipolar OECTs enable the inverter to achieve a record‐high gain (102 V/V) and associated n‐type and p‐type molecular detectors to offer real‐time and highly sensitive detection of histamine and hydrogen peroxide detection, respectively. These results indicate the effectiveness of judicious molecular design on achieving high‐performance ambipolar OMIECs, allowing the state‐of‐the‐art single‐component ambipolar OECTs for both highly integrated logic circuit and bioelectronic applications.

Black phosphorus (BP), an emerging 2D layered material, is promising for nanoelectronic applications due to its high carrier mobility and saturation velocity. A high performance ambipolar BP field‐effect transistor (FET), fully assembled from 2D materials, is demonstrated. It exhibits two‐terminal mobility of 540 cm2 V−1 s−1 for holes and 250 cm2 V−1 s−1 for electrons at room temperature. The ambipolar charge transport of the BP FET allows it to operate as a p‐ and n‐type switchable inverter with operating frequency up to 160 kHz through simply changing the polarity of the supply voltage. At the same time, the voltage gain of the inverter is higher than 1, suggesting that it is suitable for logic‐circuit applications. Moreover, it is shown that the ambipolar BP FET can function as an output‐polarity controllable amplifier through tuning of the input and supply voltages. This demonstration paves the way for future BP applications in logic circuits.

Following the unprecedented rise in photovoltaic power conversion efficiencies during the past five years, metal-halide perovskites (MHPs) have emerged as a new and highly promising class of solar-energy materials. Their extraordinary electrical and optical properties combined with the abundance of the raw materials, the simplicity of synthetic routes, and processing versatility make MHPs ideal for cost-efficient, large-volume manufacturing of a plethora of optoelectronic devices that span far beyond photovoltaics. Herein looks beyond current applications in the field of energy, to the area of large-area electronics using MHPs as the semiconductor material. A comprehensive overview of the relevant fundamental material properties of MHPs, including crystal structure, electronic states, and charge transport, is provided first. Thereafter, recent demonstrations of MHP-based thin-film transistors and their application in logic circuits, as well as bi-functional devices such as light-sensing and light-emitting transistors, are discussed. Finally, the challenges and opportunities in the area of MHPs-based electronics, with particular emphasis on manufacturing, stability, and health and environmental concerns, are highlighted.

The stability of the subthreshold swing (SS) is quite important for switch and memory applications in logic circuits. The SS in our MoS2 field effect transistor (FET) is enlarged when the gate voltage sweep range expands towards the negative direction. This is quite different from other reported MoS2 FETs whose SS is almost constant while varying gate voltage sweep range. This anomalous SS enlargement can be attributed to interface states at the MoS2–SiO2 interface. Moreover, a deviation of SS from its linear relationship with temperature is found. We relate this deviation to two main reasons, the energetic distribution of interface states and Fermi level shift originated from the thermal activation. Our study may be helpful for the future modification of the MoS2 FET that is applied in the low power consumption devices and circuits.

Highly efficient coumarin-derived colorimetric chemosensors for sensitive sensing of fluoride ions and their applications in logic circuits

Flexible manipulation of the carrier transport behaviors in two-dimensional materials determines their values of practical application in logic circuits. Here, we demonstrated the carrier-type manipulation in field-effect transistors (FETs) containing α-phase molybdenum ditelluride (MoTe2) by a rapid thermal annealing (RTA) process in dry air for hole-dominated and electron-beam (EB) treatment for electron-dominated FETs. EB treatment induced a distinct shift of the transfer curve by around 135 V compared with that of the FET-processed RTA treatment, indicating that the carrier density of the EB-treated FET was enhanced by about 1 order of magnitude. X-ray photoelectron spectroscopy analysis revealed that the atomic ratio of Te decreased from 66.4 to 60.8% in the MoTe2 channel after EB treatment. The Fermi level is pinned near the new energy level resulting from the Te vacancies produced by the EB process, leading to the electron-dominant effect of the MoTe2 FET. The electron-dominated MoTe2 FET showed excellent stability for more than 700 days. Thus, we not only realized the reversible modulation of carrier-type in layered MoTe2 FETs but also demonstrated MoTe2 channels with desirable performance, including long-term stability.

Bilayer graphene like monolayer graphene has a zero bandgap. To use as a channel material of FETs, its band gap should be open which is crucial for its application in logic circuits. Several methods have been developed to open the band gap in graphene. The simple way is cutting graphene into ribbons. In this paper, a novel structure for a dual-gated bilayer graphene nanoribbon field-effect transistor (BLGNRFET) is suggested, which merges the advantages of high and low dielectric constants. The gate insulator of FET is divided into four parts with different dielectric materials, so the proposed device is called FDI-BLGNRFET. All of the possible state of gate insulators which can happen for these four different parts are surveyed. The simulations are conducted by means of the self-consistent solution of the Poisson and Schrodinger equations within the Non- Equilibrium Green Function (NEGF) and a tight-binding Hamiltonian, in the real space approach. Regarding to the results, for the proposed FDI-BLGNRFET with K1 = K2 = 25 and K3 = K4 = 3.9, the maximum ${I_{ON}}/{I_{OFF}}$ ratio 119% higher than the conventional BLGNRFET is achieved which is still remains inadequate for getting an acceptable $({{I_{ON}}/{I_{OFF}}})$ ratio in CMOS performance.

Coumarin-based thiosemicarbazones as colorimetric and fluorescent “Turn on” chemosensors for fluoride ions and their applications in logic circuits

The advancement of integrated circuits (ICs) has been following Moore’s Law well since 1960s. For the sustaining of Moore’s Law, technologists in the microelectronics industry are, on one hand, trying to push lithography technology to the limit for making devices with smaller length scales. Extreme ultraviolet, e-beam, nanoimprint or other lithography technologies have been developed as candidate replacement technologies for the conventional optical lithography (Gwyn et al., 1998; Vieu et al., 2000; Chou et al., 1996). On the other hand, technologists are also exploring the third dimension for the 3D integration of chips (Baliga, 2004). Although the advancement of lithography technologies and 3D integration technology can keep the IC industry abreast of Moore’s Law for the next decade, the problems we will face at the end of that period are becoming visible. The emerging of nanowires/nanotubes as building blocks of ICs will bring fundamental changes to the future IC industry and offer continuance of Moore’s Law. Besides the applications in logic circuits, nanowires have very promising applications as sensing elements in highly sensitive bio/chemical/photon sensors and detectors. Nanowires are commonly grown by vapor-liquid-solid (VLS) process (Wagner & Ellis, 1964), vapor-solid (VS) process (Zhang et al., 1999), electrochemical deposition into nanoporous templates (Sander et al., 2002), and solution growth (Govender et al., 2002). In the past 20 years, nanowires of a diverse range of compositions have been produced at a relatively low cost with precisely controlled parameters including structure, size, defect, and doping. Nanowire devices such as field effect transistors (FETs) (Ju et al., 2007), single virus detector (Patolsky et al., 2004), pH sensor (Cui et al., 2001), gas sensors (Zhang et al., 2004), and photodetectors (Soci et al., 2007) have been demonstrated to show superior performance than their thin-film counterparts or even exhibit novel properties that have never been achieved by thin-film technology. However, most of the nanowire devices are limited to the demonstration of single device, not adequate for production on a large scale at low cost. Ultimately, cost and yield will decide whether nanowire devices find their way into market. Developing cost-effective means to integrate nanowires into working devices on large scales is essential for the prosperity of nanotechnology. In this chapter, we focus on progress toward nanowire device assembly technologies, which may benefit for the mass production of nanowire devices in the future. Generally, two strategies exist for the fabrication of devices from nanowires, namely, transfer pre-grown nanowires onto a surface with

Tin oxide is a promising channel material, offering the advantages of being low-cost and environmentally friendly and having a wide band gap. However, despite the high electron mobility of SnO2 in bulk, the corresponding thin-film transistors (TFTs) generally exhibit moderate performance, hindering their widespread application. Herein, we proposed a codoping strategy to improve both the electrical property and the stability of SnO2 TFTs. A comparative analysis between doped and undoped SnO2 was conducted. It is observed that taking advantage of the difference in ionic radii between two dopants (indium and gallium) and the tin ions in the host lattice can effectively reduce impurity-induced strain. Additionally, we investigated the effect of codoping content on SnO2 TFTs. The optimal codoped SnO2 (TIGO) TFTs demonstrate high performance, featuring a field-effect mobility of 15.9 cm2/V·s, a threshold voltage of 0.2 V, a subthreshold swing of 0.5 V/decade, and an on-to-off current ratio of 2.2 × 107. Furthermore, the devices show high stability under both positive and negative bias stress conditions with a small threshold voltage shift of 1.8 and -1.2 V, respectively. Utilizing the TIGO TFTs, we successfully constructed a resistor-loaded unipolar inverter with a high gain of 10.76. This study highlights the potential of codoped SnO2 TFTs for advanced applications in electronic devices.

Memristors show excellent ductility and low power consumption. They have broad applications in logic circuits, neuromorphic computing and non-volatile memory. Memristors show great potential in true random number generation (TRNG). To verify memristors' randomness, we made two kinds of memristors, measured the randomness of their delays, and investigated their different randomness mechanisms. We did thousands of experiments and verified the feasibility of making a new TRNG using these two kinds of memristors. We also found a new application of memristors to make non-linear device.

While liquid crystal elastomers (LCEs) show promise for diverse soft actuators due to their strong stimulus responsiveness, limited investigation into their light perception and processing restricts their wider use in intelligent systems. This study employs a hollow double-layer structure to design light-controlled logic soft switches based on LCEs. The design realizes digital logic circuits including AND gates, OR gates, and NOT gates, as well as an optical switch array capable of converting light signals into visualized digital signals. These light-controlled soft switches exhibit strong photothermal responsiveness (~12 s), high programmability, and excellent cyclic stability (>500 times). This research provides a new perspective on light-controlled logic soft switches and their applications in logic circuits.

At low temperatures, a mean free path of electrons in semiconductors may exceed device dimensions. Current-voltage characteristics, potentials, electrical field, and carrier distributions are calculated for a two-terminal device under such conditions when the electron transport is ballistic. Current-voltage characteristics of a ballistic FET are analyzed using an approach similar to the Shockley model. It is shown that very high drift velocities can be obtained at low voltages leading to high speed and low power consumption in possible applications in logic circuits. For example, GaAs logic devices with characteristic dimensions about a micrometer or less at 77 K will be comparable with or better than Josephson tunneling logic gates.