Functionally Undetectable Interconnect Faults in Chiplet-Based Designs

A systematic method is proposed to approach complete fault coverage for catastrophic faults in analog circuits. In the proposed method, a fault propagation graph is first created from the circuit netlist. Standard graph theory techniques are then employed to identify a minimal set of observation points (MOP) such that, by monitoring these points, complete fault coverage can be achieved, i.e., all potential catastrophic faults of the circuit can be detected theoretically. The developed method is valuable because of the increasingly critical quality requirements for modern IC applications and the lack of existing methods that can achieve sub-ppm test escapes in the state-of-the-art. A widely used benchmark circuit, a CMOS operational amplifier, is utilized to demonstrate and validate the method. Simulation results show that all catastrophic faults can be detected by monitoring the identified MOP.

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

This paper presents a low-overhead scheme for the built-in self-test (BIST) of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without degrading system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant faults are embedded in a pseudo-random sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudo-random sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Also, the proposed approach permits the use of small LFSRs for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by embedding deterministic cubes at the expense of additional bit-fixing logic. Data is presented showing how much additional logic is required for different size LFSRs.

Any FPGA structure has interconnect cells, configurable logic blocks and I/O pads. The physical path between the blocks form interconnects. The logic blocks may have both combinational and sequential circuits to perform logic functions. Here the logic blocks are assumed to have either combinational or sequential circuits which generate a single minterm or maxterm as the output. The FPGA testing is divided into interconnect and logical testing. In interconnect testing fault models are introduced in the wire connections that exists within logic blocks and these faults are propagated to the output thereby detecting the faults at interconnects. In general 2n test vectors are needed to test the single term logic function with n inputs. Here Walsh code is used to optimize the test vectors. The number of test vectors are optimized as log2(M+2), where M is number of wire connections. The test vectors are the columns of M binary numbers and the successive binary numbers are exchanged to obtain the test vectors

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs.

We use a property that distinguishes most of the undetectable faults in a circuit from detectable ones, in order to avoid targeting undetectable faults during test generation. We show that it is possible to avoid most of the undetectable faults until most of the detectable faults are detected. The test generation process is speeded-up by avoiding undetectable faults, since wasted effort expended in trying to detect undetectable faults is avoided. When all or most of the faults that remain undetected by the test generator appear to be undetectable faults, a procedure for identifying undetectable faults may be used. Detectable faults, if any such faults remain, may then be given to the test generator to obtain complete fault coverage. We study the proposed property in conjunction with test generation processes for both combinational and sequential circuits.

Faults in sequential circuits are studied. Undetectable and redundant faults under different modes of operation are analysed. Undetectable faults are split into two classes: operationally redundant faults and partially redundant faults. Operationally redundant faults are defined as faults that are never manifested as faulty output during normal operation. Partially redundant faults are defined as faults that can affect the output sequence under certain initial conditions otherwise it is undetectable. Faults in sequential circuits are, accordingly, classified into three classes: detectable, partially detectable and operationally redundant. Test generation strategies and the relation between test sequences under different modes of operation are analysed.

The configurable building blocks of current FPGAs — Logic blocks (LBs), Digital Signal Processing (DSP) slices, and Block RAMs (BRAMs) — make them efficient hardware accelerators for the rapid-changing world of Deep Learning (DL). Communication between these blocks happens through an interconnect fabric consisting of switching elements spread throughout the FPGA. In this paper, a new block, Compute RAM, is proposed. Compute RAMs provide highly-parallel processing-in-memory (PIM) by combining computation and storage capabilities in one block. Compute RAMs can be integrated in the FPGA fabric just like the existing FPGA blocks and provide two modes of operation (storage or compute) that can be dynamically chosen. They reduce power consumption by reducing data movement, provide adaptable precision support, and increase the effective on-chip memory bandwidth. Compute RAMs also help increase the compute density of FPGAs. In our evaluation of addition, multiplication and dot-product operations across multiple data precisions (int4, int8 and bfloat16), we observe an average savings of 80% in energy consumption, and an improvement in execution time ranging from 20% to 80%. Adding Compute RAMs can benefit non-DL applications as well, and make FPGAs more efficient, flexible, and performant accelerators.

This paper describes a test generation procedure that produces functional broadside tests for logic blocks whose primary input sequences are constrained. The constraints are created during functional operation by logic blocks that drive the logic block under consideration. Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where delay faults are detected. Test generation procedures for functional broadside tests typically assume that the primary input sequences are unconstrained during functional operation. This paper shows that the constraints, which are imposed by a logic block driving the primary inputs of another block, can be time dependent and difficult to represent compactly. The test generation procedure described in this paper addresses this issue by separating the problem of test generation into the generation of constrained primary input sequences for the block under consideration, and the extraction of functional broadside tests from these sequences.

As IC densities are increasing, cluster-based field programmable gate arrays (FPGA) architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-base architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high-density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis. This technique enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intracluster configurations separately from extracluster configurations, thereby improving the efficiency of the configuration definition process. The cornerstone of this work is the concise expression of the detectability conditions of each fault and the distinguishability conditions of each fault pair. By guaranteeing that both intracluster and extracluster configurations have several test transparency properties, hierarchical fault detectability is ensured.

Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

This paper introduces a new approach to pattern dependent static current estimation in logic blocks. A static current model is first developed at the transistor level and then extended to the logic gate level and logic block level. Using these static current models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which the cells are generated and sized dasiaon the flypsila, driven by specification and targeted technology. Across several MCNC benchmarks, the worst case mean accuracy of the estimation methodology compared to SPICE is 2.4%. The runtime of the proposed methodology was also on average 43 times faster than SPICE.

This paper addresses the problem of generating deterministic test patterns via a cost-efficient self-test circuitry. The proposed solution is based on primitive linear feedback shift registers (LFSR) and a mapping of their outputs on the inputs of the circuit under test. By construction, an exhaustive enumeration of all LFSR states ensures a complete stuck-at fault coverage. For the computation of the mapping function two approaches will be discussed that are based on an tuned ATPG algorithm or alternatively on a given deterministic test pattern set. Experimental data with over 30 benchmark circuits underline the efficiency of these approaches; with only a few exceptions a LFSR of length 20 is sufficient to guarantee complete fault coverage.

A test generation procedure is now presented which utilizes the hierarchical circuit and fault models developed in the previous chapter. It aims to exploit the possibility of detecting a significant percentage of the SSL faults by generating tests for total bus faults in the high-level model of a circuit. By effectively merging sets of SSL faults that can be tested in parallel, the number of target faults is reduced, as is the overall test generation effort. Tests for faults that cannot be directly handled can then be obtained by applying the same test generation procedure to a gate-level model of the circuit. Thus, the test generation technique presented here is truly hierarchical, i.e., invariant with respect to the level of the circuit and fault model used, a feature that sets it apart from most other test generation procedures. Moreover, at the gate level total bus faults are the same as SSL faults, implying that the hierarchical test generation technique allows us to obtain complete SSL fault coverage while generating tests for total bus faults only. Experimental results for sample circuits are presented, which show that this approach results in complete test sets for SSL faults that are almost always smaller than those generated by conventional methods.

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.