Functional test generation using binary decision diagrams

Abstract

This paper proposes an extension to the D-algorithm, for integrated circuits described using binary decision diagrams. An LSI/VLSI circuit is modeled as a network of interconnected modules such as counters, registers, ROMs, RAMs, decoders, and multiplexers. The individual modules are described at the functional level using binary decision diagrams. A fault model is developed at the functional level quite independent of the implementation details of the individual modules in the chip. A generalization of the D-algorithm is proposed which takes the module-level model and the functional description of the modules as parameters, and generates tests to detect the faults in the fault model. Algorithms which perform the basic operations of the test generation procedure, on the functional modules, are also presented.