Functional Fault Impact Probability Prediction using Spatio-Temporal Graph Convolutional Network

This paper deals with the design and implementation of a universal functional test generator for VLSI circuits, such as microprocessor and processor cores. Our approach to test generation—the functional test generation method–is based on knowledges and functional description of VLSI systems at functional VHDL level and the algorithm for automatic generation of test (normal executable test sequence of instructions) and arrangement, is used in very flexible and effective tool - functional test generation software system. Also a short methodology overview for the test synthesis of VLSI circuits using an automated process of the VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG) is presented. The determination of the test efficiency of instructions mixes is discussed.KeywordsAutomatic Functional Test Generation (AFTG)Test SynthesisMixed TestVHDL TestbenchIdentification Test MethodThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

An implementation-dependent functional testing methodology is developed for pipelined CPU implementations. The magnitude of pipeline design errors is established through the study of the design log of a commercial computer system. A model for determining the correctness of the execution of a machine language program is developed. The basis for functional pipeline test generation, the dependency graph, is introduced. A quantitative analysis of the number of dependency arcs exercised by a given instruction stream is developed. Techniques to reduce the complexity are also introduced. A methodology for generating pipeline functional test modules for a pipelined implementation is developed. Application of the methodology to a military standard computer architecture, the MIL-STD-1750A, is described. The results for the test generator, called AUTOGEN, show two orders of magnitude reduction of the test length over the standard comprehensive architectural verification program.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

Functional test generation based on word-level SAT

Developments in electronic/fluidic microsystems are progressing rapidly. The ultimate goal is to deliver products in the 10,000 fluidic reaction-wells range. Exciting applications include massive parallel DNA analysis and automatic drug synthesis. Until now, only functional testing has been used to “guarantee” the quality of micro-fluidic systems after manufacturing. In this paper, defect-oriented test approaches developed in analogue fault modeling and simulation have been used to predict for the first time the faulty behavior of micro-electronic fluidic microsystems. The modeling is targeted for use in complex electronic/fluidic microsystems employing commercial microsystem CAD tools. It enables a measure for the quality of these systems based on the performed (functional) tests and can be a guide for future test-stimuli generation and yield prediction.

We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLAs are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark PSM's from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests.

Scan-based tests may lead to overtesting of delay faults by bringing a circuit to states that the circuit cannot enter during functional operation. Functional broadside tests address this issue by using reachable states as scan-in states. Different strategies for generating functional broadside tests have been studied and implemented by academic tools. The main challenge that these procedures address is the identification of reachable states that are useful as scan-in states. This paper describes the generation of functional broadside tests using a commercial test generation tool. Our results demonstrate that it is possible to generate functional broadside tests without requiring any modifications to the commercial tool, and using the tests that the tool produces to obtain reachable states. This is expected to enable the generation of functional broadside tests for state-of-the-art designs that cannot be handled by academic tools. To demonstrate this point, we apply the procedure to two large logic blocks of the OpenSPARC T1 microprocessor.

Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where they detect delay faults. One of the challenges in the generation of functional broadside tests is test compaction. Existing dynamic compaction approaches for scan tests are not applicable to functional broadside tests, and static compaction approaches are limited in the level of test compaction they can provide. The solution suggested in this paper has two new properties. (1) Instead of attempting to compact functional broadside tests, test compaction is applied to a functional test sequence from which functional broadside tests are extracted. The compact sequence yields a compact functional broadside test set. (2) Compaction of the functional test sequence is performed without sequential fault simulation. This is possible since test compaction does not have to preserve the fault coverage of the functional test sequence. The solution is developed in the scenario where the primary input vectors of a circuit are not constrained during functional operation. Experimental results for benchmark circuits demonstrate its ability to compact a functional broadside test set for transition faults.

The paper presents functional delay test generation approach for non-scan\n synchronous sequential circuits. The non-scan sequential circuit is\n represented as the iterative logic array model consisting of k copies of the\n combinational logic of the circuit. The value k defines the number of clock\n cycles. The software prototype model is used for the representation of the\n function of the circuit. The faults are considered on the inputs and on the\n outputs of the model only. The random input stimuli are generated and\n selected then according to the proposed approach. The experimental results\n demonstrate the superiority of the delay test stimuli generated at the\n functional level using the introduced approach against the transition test\n stimuli obtained at the gate level by deterministic test generator. The\n functional delay test generation approach especially is useful for the\n circuits, when the long test sequences are needed in order to detect\n transition faults.

We investigated the influence of the random generation methods to the results of the functional delay test generation. There are the three possibilities: random generation of values 0 and 1 when the probability for the appearance of each value is 50% in every bit of test pattern; random generation of large integer values, which then are split into the sequences of 0’s and 1‘s according to the rules of the conversion of the decimal number to the binary number; anti-random generation when the presence of the earlier generated patterns is taken into account. We adopted the anti-random generation for the functional delay faults. The obtained results of the investigation indicate that the random generation has the direct influence to the results of the functional delay test generation. The largest coverage of transition fault is obtained when the anti-random generation is employed.

Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states offline.

The selection of test points is one of the key steps for electronic systems on prognostic and health management (PHM). Parameters of reasonable test points can characterize the fault features of electronic systems and provide effective input information for diagnosis and prognosis. In this chapter, an improved method of test point selection for analog electronic systems on diagnosis and prognosis is proposed and a case study is presented. The proposed method includes several steps: (1) fault risk analysis: determine susceptibility areas for the electronic system based on environmental stresses analysis and life analysis; (2) functional simulation analysis: based on the circuit schematic diagram, establish the functional simulation model for the system and list all accessible nodes, then identify the relationship between nodes and faults by using correlation models; (3) fault simulation analysis: Combine with the previous analysis of failure modes and mechanisms and set corresponding faults in the functional simulation software; (4) Comprehensive evaluation and selection: evaluate fault simulation data of each test point, and select appropriate test points for the system. The presented method has the following features: considering the specific product condition and failure mechanisms, focusing on high-risk mechanisms, and basing on fault simulation to revise testability model to make it closer to the real fault situations.KeywordsTest point selectionDiagnosisPrognosticSimulationAnalog electronic systems

Renewable Energy Sources are an effective alternative to the atmosphere-contaminating, rapidly exhausting, and overpriced traditional fuels. However, RESs have many limitations like their intermittent nature and availability at far-off sites from the major load centers. This paper presents the forecasting of wind speed and power using the implementation of the Feedforward and cascaded forward neural networks (FFNNs and CFNNs, respectively). The one and half year’s dataset for Jhimpir, Pakistan, is used to train FFNNs and CFNNs with recently developed novel metaheuristic optimization algorithms, i.e., hybrid particle swarm optimization (PSO) and a Bat algorithm (BA) named HPSOBA, along with a modified hybrid PSO and BA with parameter-inspired acceleration coefficients (MHPSO-BAAC), without and with the constriction factor (MHPSO-BAAC-χ). The forecasting results are made for June–October 2019. The accuracy of the forecasted values is tested through the mean absolute error (MAE), mean absolute percentage error (MAPE), and root mean square error (RMSE). The graphical and numerical comparative analysis was performed for both feedforward and cascaded forward neural networks that are tuned using the mentioned optimization techniques. The feedforward neural network was achieved through the implementation of HPSOBA with a mean absolute error, mean absolute percentage error, and root mean square error of 0.0673, 6.73%, and 0.0378, respectively. Whereas for the case of forecasting through a cascaded forward neural network, the best performance was attained by the implementation of MHPSO-BAAC with a MAE, MAPE and RMSE of 0.0112, 1.12%, and 0.0577, respectively. Thus, the mentioned neural networks provide a more accurate prediction when trained and tuned through the given optimization algorithms, which is evident from the presented results.