From vulnerability to robustness: Radiation-hard isolation for BPR-enabled stacked nanosheet CFETs

A deterministic reaction-diffusion–drift model is used for the time kinetics of bulk gate insulator trap generation in p-channel Field Effect Transistors (FETs) under inversion stress. The consistency of the deterministic and stochastic versions of the model is shown. The model is independently validated using stress-induced leakage current data from various reports. The model is incorporated into the already existing bias temperature instability (BTI) analysis tool framework and validated using negative BTI data. The measured data from FinFETs having different channel material, substrate type, gate insulator process, and fin length, as well as gate-all-around stacked nano sheet (GAA-SNS) FETs are modeled.

In this study, the vertically stacked Nano-sheet at the gate length of 10nm is considered. The Nano-sheet is vertically stacked and stacked with gate oxide material of SiO2 with HfO2 each of 1nm thickness. Three fins vertically stacked structures were examined for performance and compared same model at lower and higher voltages. The performance comparative parameters are drive currents and short channel effects, trans-conductance (gm), and output conductance device are considered. All simulations are carried out using the platform of professional V-TCAD device simulator.

Silicon height, width, and number of 3D stacked nanosheet layers are optimized in this paper to achieve lower power consumption, enhanced integration density, and higher performance with gate all-around (GAA) 3D stacked nanosheet transistors. Electrical characteristics of vertically stacked nanosheet transistors are compared with FinFETs under equal silicon area and ON current constraints. Assuming a tight vertical silicon sheet pitch of 5nm, test circuits with the vertically stacked nanowires provide comparable speed with active mode energy consumption, silicon area, and idle mode leakage power consumption savings of up to 40.24%, 21.81%, and 63.58%, respectively, as compared to FinFETs in a 5nm CMOS technology.

In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay (tdelay) and dynamic power (Pdyn) are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the τdelay and Pdyn are improved at the same Pdyn (50 μW) and tdelay (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.

As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and compared the electrical characteristics of single-NS and stacked-NS structures. The performance of the multi-gate and gate-all-around transistors was then further analyzed. The stacked gate-all-around thin-film transistor exhibited superior performance and excellent temperature design flexibility. In brief, the stacked gate-all-around structure for thin-film transistors structure has the potential to overcome the challenges associated with downscaling.

For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this work, we demonstrate a novel integration scheme for evaluating the inner spacer reliability by completely oxidizing the Si channel. The inner spacer TDDB reliability is also shown to be robust, which is essential to support the continuous aggressive device scaling.

In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( 7.28×1011 ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by 1.11×101 and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by 2.34×10−2 A and improves the switching ratio by 2.90×101. An increase in the source doping level from 1×1020 to 5×1020 cm−3 results in a 1.07×102 decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is 1×1017 cm−3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

In this paper, self-heating effect in newly introduced stacked nanosheet gate-all-around transistor is investigated and discussed, and several architecture parameters such as metal gate thickness, number of channels, thermal conductivity of ILD and channel thickness affecting thermal reliability of nanosheet FET are studied through simulations. It is illustrated that nanosheet FET shows great lattice temperature variations and thermal resistance fluctuations from changes in such architecture parameters, and these can be mitigated by increasing thermal conductivity of ILD, and metal gate thickness.

Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO 2 -based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F2/N is achieved (‘N’ being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 104 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach.

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.

The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with different etch conditions in order to induce variations in the indent. It was found that both scatterometry in conjunction with Spectral Interferometry and novel interpretation algorithms as well as TEM calibrated LE-XRF are suitable techniques to quantify the indent. Machine learning algorithms enabled an additional solution path by combining LE-XRF data with scatterometry spectra therefore avoiding the need for a full optical model.

In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied. By comparing off-state leakage current, short channel behavior and effective capacitance (Ceff) for both schemes, we show that BDI could potentially provide: 1) good immunity of sub-channel leakage due to process variation (from parasitic "fat-Fin" which is unique in Nanosheet structure); 2) power-performance co-optimization.