FPGA Implementation of Feature Extraction and Neural Network Classifier for Handwritten Digit Recognition

Abstract

FPGA (Field Programmable Gate Arrays) implementation of an off-line handwritten digit recognition system based on elastic meshing directional feature extraction and integrated neural network classifier is proposed in this paper. Elastic meshing directional feature extraction is used to extract the feature of normalized 32*16 handwritten digit images. Integrated neural network classifier with BP (back-propagation) learning algorithm is designed as classifier. The pipeline technology and multi-buffer technology are used in the FPGA implementation of elastic meshing directional feature extraction. FPGA implementation architecture of neural network computing unit and integrated neural network classifier is proposed in this paper. Experiment shows that compared with software-based implementation, FPGA-based system can greatly speed up off-line handwritten digit recognition and is suitable for application in some real-time situations where high process speed and portability are required.