FPGA Design and Implementation of a Real-time Subpulse Processing Architecture for Noise Radars

Abstract

Noise radar is the general term used to describe pulse compression radar systems that employ realizations of a given stochastic process as transmit waveforms. Despite several features, the low Doppler tolerance of such signals induces mismatch losses that can severely deteriorate the system’s performance, specially when long duration pulses are required. A possible solution to circumvent such issue is to perform a subpulse processing technique on the received signal. The latter reduces the mismatch loss at the expense of an increase in the computational load. In the present work such trade off is better addressed, considering a real-time application. The proposed architecture is verified in a co-simulation environment using Xilinx®System Generator tool and implemented on reconfigurable hardware, i.e., a Xilinx Field Programmable Gate Array (FPGA) is taken into consideration. Timing, resources consumption and the trade offs related to accuracy, hardware area and performance are then investigated.