Abstract
Sequence alignment have been optimized using several techniques in order to accelerate the computation time to obtain the optimal score by implementing DP-based algorithm into hardware such as FPGA-based platform. During hardware implementation, there will be performance challenges such as the frequent memory access and highly data dependent in computation process. Therefore, investigation in processing element (PE) configuration where involves more on memory access in load or access the data (substitution matrix, query sequence character) and the PE configuration time will be the main focus in this paper. There are various approaches to enhance the PE configuration performance that have been done in previous works such as by using serial configuration chain and parallel configuration chain i.e. the configuration data will be loaded into each PEs sequentially and simultaneously respectively. Some researchers have proven that the performance using parallel configuration chain has optimized both the configuration time and area.
Highlights
Protein sequence alignment searches for sequence homology between query and subject sequence
The data bus connected to all circular buffers output and broadcast the requested substitution matrix column corresponding to the query sequence resides in each processing element (PE)
This section discusses the FPGA-based implementation performance with varies methods used of PE loader which had been reviewed in previous section
Summary
Protein sequence alignment searches for sequence homology between query (unknown sequence) and subject sequence. For the case of pairwise sequence alignment, a query sequence of length n with sequence characters of ( x1x2 xn ) and a subject sequence characters of ( y1 y2 ym ) of length m, is The Smith-.
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