FPGA based custom accelerator architecture framework for complex event processing

Abstract

Complex Event Processing (CEP) is an emerging field in high performance computing paradigm where real time (low latency) computing capability is expected over big data processing (high throughput). Significant number of software architectures have been developed to improve the throughput while reduce the latency but maintaining of the both aspects reaches the limits of the software platforms. This paper proposes a novel custom hardware accelerator architecture framework for CEP in big data domain. The proposed design improves the throughput performance more than 10 times over the software counterpart while keeping the latency value at less than 100 nano seconds. Same Structured Query Language(SQL) type queries used in reference software architecture were used to improve the flexibility. A query compiler based on the same query language grammar was designed to convert the queries in to Hardware Description Language(HDL) modules. All modules were parameterized to improve the scalability of the design. Those generated modules were synthesized through vendor tools and programmed in to Field Programmable Gate Array(FPGA) platform in order to implement the system. Proposed hardware architecture framework was verified using a sensor network data set of a football field and the results were compared with software counterpart to show the performance improvement.