FPGA architecture for text extraction from images

Abstract

Image processing is a computationally intensive operation and it is typically done in software using CPU processing power that is readily available these days. The applications that make use of image processing require expensive and powerful CPUs to perform real-time operations. Hence a low cost FPGA based image processing solution becomes useful. This eliminates the need for powerful CPUs and at the same time real-time processing can be achieved relatively easier. This paper proposes an algorithm for extracting text information from images. With the help of FPGA, the pixels can be pipelined or processed in parallel in order to achieve increased processing speed. The gray scale conversion is done on the input image followed by image binarization. In order to extract text from input image, morphological close operation and connected component analysis are performed. The ultimate aim and motivation of this paper is detected and extract the words and letters from the input image with efficient hardware architecture. Simulation is done using VHDL coding and the analysis and synthesis results are carried out using the device XC7VX330T of Virtex7 family. FPGA provides higher flexibility since the architecture can be easily upgraded to meet the requirement. It is observed that area and power minimization is obtained by implementing an optimized design using this algorithm.