Foreword: Special Section on Advances in Heterogeneous Integration for Neuromorphic Computing

The International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK) is a flagship conference of ASME Electronic and Photonic Packaging Division (EPPD). It has served as an international forum within the ASME society to share and exchange latest progresses in the research, development, and applications of electronic and photonic packaging since 1992. The aim of ASME Journal of Electronic Packaging (JEP) Special Section for InterPACK is to publish outstanding papers from technical tracks of InterPACK2021, which was held virtually amid COVID-19 pandemic worldwide. This Special Section of the ASME JEP publishes nine papers presented at the InterPACK2021 in the areas of electronics and photonics packaging, micro-electronics reliability, and advanced thermal management from the silicon, package, to data center level. All nine papers published in this JEP Special Section for InterPACK2021 went through a standard peer-review process for journal papers published by ASME.The micro-electronics industry is facing challenges to meet demanding performance and functional needs of high-performance computing (HPC), artificial intelligence (AI), 5 G/mm Wave, and power electronic devices. In order to close this gap, in parallel with new breakthroughs in advancing silicon node, the semiconductor industry is also embracing advanced integrated circuits (IC) packaging technologies, including heterogeneous integration, 2.5D/3D IC packaging, chiplet, additive manufacturing, novel modeling and characterization techniques, and others. This Special Section reflects latest progresses in the IC packaging by publishing nine papers presented at ASME InterPACK2021. We gratefully acknowledge all the authors who have revised their original conference papers for this Special Section and the reviewers who have spent tremendous time and efforts to help improve overall quality of the papers for this Special Section. We also would like to thank the ASME JEP Editor-in-Chief (EIC), Professor Shi-Wei Ricky Lee for his guidance and support, and the assistant to EIC, Dr. Jeffery Lo for his help in this journey.

This Special Section of the ASME Journal of Electronic Packaging (JEP) is dedicated to state-of-the-art advancements made in nanoscale and microscale thermal energy transport across a variety of electronics cooling platforms. This topic has quickly emerged as a central issue in electronics packaging, particulary as device length scales approach the mean free path of heat energy carriers and traditional cooling techniques achieve maximum cooling effectiveness. Further, the nanoscale and microscale regimes present unique challenges to dissipating heat from electronics because the physics of energy transport transitions from those described by continuum mechanics to physics that require insight into the way in which quantized microscopic energy carriers traverse within solids and fluids.The set of papers collected as part of this work span a wide variety of areas and provide the readership of JEP with a sampling of important topics in this field. For example, a comprehensive review paper is included to discuss the impacts of nanoscale thermal transport on the performance of emerging devices, such as those used in neuromorphic computing and state-of-the-art power electronics. The paper also provides readers with an exhaustive accounting of how nanostructuring impacts material thermal properties and heat flow across interfaces, and provides individual perspectives on leading devices from 12 experts across 10 separate institutions. The special section also contains invited papers from research groups led by Dr. Nenad Miljkovic (University of Illinois at Urbana Champaign) and Dr. Ankur Jain (University of Texas at Arlington), which describe the development of modular heat sinks for thermal management and backside infrared thermal imaging of semiconductors, respectively. Finally, two papers are included that: (1) evaluate the structural properties of alumina-based ceramic pastes for electronics operating at high temperatures and (2) interrogate the impact of a microchannel/jet impingement cooling technique on the operating conditions of data center servers.It is my hope that such research becomes commonplace in JEP, particularly as the impacts of nanostructuring become more pronounced with continued device miniaturization. Please enjoy the series of papers presented in this special section, and thank you for choosing to read the ASME Journal of Electronic Packaging.

The articles in this special section were presented at the 2019 IEEE VLSI Test Symposium (VTS) that was held in Monterey, CA. The 2019 VTS Conference laid particular emphasis on enlarging its scope by soliciting submissions on testing, reliability, and security aspects on the following hot topics: approximate computing, neuromorphic computing, and quantum computing.

The papers in this special section focus on emerging trends and computing paradigms for testing, reliability and security in future VLSI systems. With the rapid advancement of computing technologies in all domains (i.e., handheld devices, autonomous vehicles, medical devices, and massive supercomputers), testability, reliability, and security of electronic systems are crucial challenges for the safety of human life. Emerging technologies coupled with new computing paradigms (e.g., approximate computing, neuromorphic computing, in-memory computing) are together exacerbating these problems posing significant challenges to researchers and designers. To address this increased complexity in the hardware testing, reliability, and security domains, engineers must employ design and analysis methods working at all levels of abstraction, starting from the system level down to the gate and transistor level.

Functional materials are an integral component of a myriad of devices taken for granted by modern society. Technologies that allow these materials to be fabricated and integrated more easily and economically, as well as clever device designs and innovative applications are key to their wide adoption. It is thus perhaps no wonder that, with its focus on technology-related applied materials research, Advanced Materials Technologies has achieved such good traction within the research community since its launch in 2016. 2019 is proving to be an exciting one for Advanced Materials Technologies. A few weeks ago, the journal received its first full Impact Factor (IF) of 5.395.1 This equates to a 17% increase over last year's partial IF (4.622). Table 1 lists the ten Advanced Materials Technologies articles published in 2016 or 2017 that were cited most in 2018. These hot topics – flexible and stretchable energy conversion and storage devices, sensors, actuators, photonics, electromagnetic interference (EMI) shielding and practical fabrication technologies – are representative of the wide-ranging, multidisciplinary areas of research covered by the journal. For a taste of the most popular papers we have published more recently take a look at our “Best of 2018” – free to access for a limited time – and make sure you don't miss our “cover art gallery” with the most stunning cover images of 2018. The increasing popularity of Advanced Materials Technologies is evident by submissions to the journal, which have grown strongly over the past year. Indeed, we are on track to receive over 1000 manuscripts this year. To ensure our authors continue to enjoy the best possible service, we recently strengthened our peer review editorial team with the addition of Dr. Marco Squillaci and Dr. Valentina Lombardo. We also welcomed Prof. Michael Dickey (North Carolina State University) to the International Editorial Advisory Board. Other highlights this year include an “Advanced Intelligent Systems” Special Series, consisting of invited-only articles that showcase the outstanding achievements of leading international researchers working in the field of intelligent systems. Topics featured include robotics, the human-machine interface, smart and responsive materials, smart sensing systems, neuromorphic computing, and programmed self-assembly. This series proved so successful that in May we launched a new premium open access journal Advanced Intelligent Systems, a general science and engineering journal that covers these research areas and more. Papers that demonstrate a holistic, systems approach, incorporating both “hard” and “soft” intelligence, are prioritized. Check out the first issue here and submit your paper now to take advantage of free publication throughout 2019. The power of microfluidic technologies for the robust and customizable production of functional materials is illustrated in the June Special Issue of Advanced Materials Technologies devoted to “Microfluidics”, guest-edited by Prof. Andrew deMello (ETH Zürich), co-chair of the Editorial Advisory Board. A Special Section in the May issue on “Interface Engineering in Organic Devices” guest edited by Paolo Samorì and Fabio Biscarini demonstrates how optimizing the design of interfaces can enhance the overall performance of devices. In further news from the wider Advanced journals group, the use of an ORCID identifier is now required for submissions to our journals. With pre-print servers playing an increasingly important role in the early dissemination of unpublished results, all Advanced journals now welcome submissions previously posted on pre-print servers. We hope you enjoy reading the research published within the pages of Advanced Materials Technologies as much as we do. In collaboration with you — our authors, reviewers and Advisory Board members — we look forward to disseminating many more important technological advances, the full impact of which remains to be discovered.

: A Liquid Cooled Heat Sink with Through Electrical Vias was designed fabricated and tested. The Heat Sink was designed for use in 3D stacks of high heat producing multichip modules. The report covers design considerations, the fabrication process and measured performance achieved A special section compares the Heat Sink performance to an equivalent diamond heat sink. A second special section discusses the economics of high volume production of the Heat Sink. Important performance results include: (1) Power Density of 5OW/cm2 with temperature rise of 15C. (2) 100 thru vias per sq cm (3) Thickness of 1.25mm.

Over the past two decades, 3D techniques combined with heterogeneous integration, combining different functions and materials, have emerged as a key enabler for overcoming the physical and scaling limits of traditional 2D integration. These approaches are now expanding across multiple domains, including CMOS, memories, photonics, imagers, and RF systems, with the aim of delivering next-generation integrated systems for advanced computing (AI), analog/RF, and imaging applications. In this presentation, we will explore the fundamental techniques, recent advancements, and some challenges associated with achieving integration. Special emphasis will be placed on the role of hybrid bonding and sequential 3D integration schemes, as well as their implications for energy efficiency, device performance, and system-level innovations.3D integration has transitioned from a niche research area to a cornerstone technology in microelectronics, driven by its potential to address high density interconnect and traditional 2D scaling bottlenecks for several applications and enable heterogeneous integration at unprecedented scales. At the heart of this technological evolution are advanced schemes such as wafer thinning, Through-Silicon Vias (TSVs), hybrid bonding, and sequential 3D integration techniques. These techniques have been pivotal in shrinking the interconnect length, reducing latency, and enhancing data bandwidth in computing systems. In parallel, developments in wafer-to-wafer, die-to-wafer, and chiplet integration are enabling the seamless merging of diverse materials enabling functionalities such as logic, memory, photonics, and RF. Compact form factors are achieved enabling to boost performances of the most demanding applications such as Artificial Intelligence or Tb/s transceiver applications [1].Recent studies highlight significant progress in hybrid bonding technology, which achieves high-density interconnects at the submicron scale, thereby optimizing power delivery and thermal management in stacked devices [2]. Meanwhile, sequential 3D integration [3][4] where layers of transistors are fabricated sequentially on the same substrate, is emerging as a game-changing paradigm. It promises ultra-high-density integration with minimal parasitics, creating new opportunities for energy-efficient and high-performance systems. Several applications are foreseen including C-FETS, memories and imagers [5] .Photonic interconnects will enter in next generation 3D IC integration, addressing challenges in data bandwidth, power consumption and signal integrity and enabling photonic interposers for next generation of components for data centers and communication systems [7]. Similarly, RF [8] and analog domains [9] benefit from 3D stacking by improving front-end module integration with specific materials (III-V, HR, ...), leading to enhanced performance and higher frequencies.Despite these achievements, significant challenges remain. Thermal dissipation is a critical bottleneck [10] , particularly in densely 3D stacked architectures where hotspots can severely impact reliability and performance. Moreover, the mechanical stresses induced during bonding and processing can affect device yield and long-term stability. Our recent work in advanced thermal management and stress engineering underscores the need for interdisciplinary approaches to address these challenges. Solutions such as microfluidic cooling, novel materials for thermal interface layers and specific bonding technologies are being actively explored. Furthermore, while heterogeneous integration is currently feasible at the wafer scale—such as wafer-to-wafer hybrid bonding, which is already in mass production—expanding application fields will require advancements in die-to-wafer integration techniques.Looking ahead, the convergence of 3D integration with emerging paradigms such as neuromorphic computing, quantum technologies, multispectral and smart imagers, and advanced packaging promises to redefine system design at all levels. The synergy between 3D technologies and heterogeneous integration of advanced materials, such as 2D semiconductors, III-V, ferroelectric or oxide semiconductor [11] materials, further expands the horizon for innovation.In conclusion, 3D integration has proven to be a transformative force in microelectronics, offering pathways to overcome traditional limitations and unlock new performance dimensions. Intensive researches worldwide continues contribute to push the boundaries of what is possible, paving the way for smarter, more efficient, and highly integrated systems.

Over the years transistor size is reduced such that now we are on the edge of Moore's law. To overcome this problem and to feed the need of better processors, multichip packaging (3D) technologies have evolved as well as new approach of computer architectures, complimentry to existing one, have developed. A major component of 3D IC is Through Silicon Via. Through-silicon vias (TSVs) directly connects die-to-die stacked structures. In the process parasitics of the IC is also changed. In this paper, a TSV structure is generated and analyzed in HFSS with a view to understand its parasitics. And the same is compared to interconnects used in equivalent 2D IC. ITRS roadmap provides standardization in silicon dimensions. Following these standards, a model of TSV is generated and simulated in HFSS to analyze, measure impact of TSV on capasitance, inductance, resistace as well as crosstalk. High density, effectively packed silicon devices can be manufactured using TSV technique. In Neuromorphic computing (NC), processing and storing of data is done at the same place. NC plays key role in making faster processors for next generations of computers as well as in making of dedicated hardware for ML, AI applications. The paper mentions possiblities of use of TSV to creat dedicated Neuromorphic components and its effect.

Abstract: This book explores the transformative convergence of neuromorphic engineering and next-generation semiconductor technologies in driving the AI revolution. As conventional computing architectures encounter scalability and efficiency limits, intelligent silicon—engineered to mimic the brain’s neural structures—emerges as a promising paradigm for achieving ultra-low-power, real-time AI processing. The book examines state-of-the-art advancements in neuromorphic chips, memristive devices, 3D integration, and in-memory computing that enable parallel processing, adaptive learning, and energy-efficient computation. It further analyzes how innovations in semiconductor fabrication, materials science, and heterogeneous integration are catalyzing the development of intelligent hardware platforms tailored for edge AI, robotics, autonomous systems, and brain-computer interfaces. Through a multidisciplinary lens, the study outlines key challenges, technological milestones, and future trajectories, offering strategic insights into how intelligent silicon can redefine AI hardware, accelerate innovation, and support sustainable computational infrastructures. Keywords: Neuromorphic engineering, intelligent silicon, semiconductors, AI hardware, memristors, in-memory computing, edge AI, brain-inspired computing, low-power electronics, intelligent chips, hardware acceleration, parallel processing, 3D integration, cognitive computing, next-generation computing

Abstract: This research paper explores the transformative convergence of neuromorphic engineering and next-generation semiconductor technologies in driving the AI revolution. As conventional computing architectures encounter scalability and efficiency limits, intelligent silicon—engineered to mimic the brain’s neural structures—emerges as a promising paradigm for achieving ultra-low-power, real-time AI processing. The paper examines state-of-the-art advancements in neuromorphic chips, memristive devices, 3D integration, and in-memory computing that enable parallel processing, adaptive learning, and energy-efficient computation. It further analyzes how innovations in semiconductor fabrication, materials science, and heterogeneous integration are catalyzing the development of intelligent hardware platforms tailored for edge AI, robotics, autonomous systems, and brain-computer interfaces. Through a multidisciplinary lens, the study outlines key challenges, technological milestones, and future trajectories, offering strategic insights into how intelligent silicon can redefine AI hardware, accelerate innovation, and support sustainable computational infrastructures. Keywords: Neuromorphic engineering, Intelligent silicon, Semiconductors, AI hardware, Memristors, In-memory computing, Edge AI, Brain-inspired computing, Low-power electronics, Intelligent chips, Hardware acceleration, Parallel processing, 3D integration, Cognitive computing, Next-generation computing

To address the inherent “memory wall” bottleneck of the von Neumann computing architecture and meet the growing demand for high-energy-efficiency non-volatile storage, ferroelectric memory technology is regaining widespread attention from both academia and industry. However, traditional perovskite-based ferroelectric materials, such as lead zirconate titanate (PZT), face inherent limitations in CMOS process compatibility and environmental regulations, making seamless integration with advanced logic processes challenging. In recent years, perovskite-structured nitride ferroelectric materials, exemplified by aluminum scandium nitride (AlScN), have emerged as a leading alternative solution. Their lead-free nature, excellent thermal stability, and potential compatibility with back-end-of-line (BEOL) processes offer critical opportunities for developing next-generation memory, neuromorphic computing, and electronics for extreme environments. This paper aims to systematically review the research background and core advantages of nitride ferroelectric materials relative to traditional materials. It discusses key challenges in material preparation and device integration, elucidates the correlation mechanisms between microstructure and macroscopic properties, and introduces representative device architectures and application prospects based on this material system. Finally, it presents outlooks on material engineering, interfaces and reliability, device architecture innovation, and heterogeneous integration with emerging semiconductors.

Recent advances in AI bring great challenges on the computing hardware. Memristor based neuromorphic computing can improve the computing density and energy efficiency significantly. However, how to integrate memristive materials and design mixed circuit with advanced CMOS platform is a key challenge. In this presentation, I will talk about our recent progress on heterogeneous integration of memristor and MOSFET. Million-level one-transistor-one-resistor (1T1R) cells can be integrated on a chip. Then I will discuss the co-design technology for memristor/MOSFET mixed circuits. A general purpose neuromorphic computing chip was designed and fabricated to process deep neural networks. I will also introduce our new hybrid training method for eliminating the accuracy loss caused by device variations.

Ultra-high density 2.5/3D heterogeneous integration has been considered an essential solution for rebooting computation applications like high performance computing, machine learning, and brain-mimicking neuromorphic computing, in both cloud and edge modes. Interposers with active auxiliary circuitry such as tunable power distribution network (PDN), phase locked loops, active signaling equalizers/ buffers, and even neuromorphic units, are emerging as much more attractive and flexible platforms than passive interposers for these applications. In this paper, an active interposer conception acting as a platform for heterogeneous integration of logic, memory and neuromorphic computing circuits, is proposed for rebooting computation purpose, featuring functioning units such as active PDN, data switching and signal conditioning circuits, and neuromorphic units based on so-called neural TSVs. New features such as pulse operation of neuron circuit and high speed data switching may induce new power integrity issues. Fortunately, the introduction of neural TSVs with large capacitance may also acting as the in-situ decoupling capacitors whose value can be modulated by the switching on/off of the MOSFETs associated with the neural TSVs in the same neuron cell, and thus a compact and tunable PDN can be constructed, whose impedance and anti-resonance characteristics may be reconfigured flexibly for an optimal power distribution and minimal simultaneous switching noise. Principles are disclosed and compact circuit modeling is set up for the PDN. Circuit and full-wave simulation results are demonstrated, confirming the conception and its effectiveness.

This paper investigates the opportunity and challenges of 3D silicon photonic electronic integrated circuits (3D EPICs) scaling to wafer-scale and beyond. The continuing demand for more data and information is driving new computing, communications, imaging, and information processing at higher throughput and energy-efficiency at lower manufacturing cost. The newly developed 3D silicon photonic devices including vertical U-turns and vertical lightpipes enable through-silicon-optical-vias (TSOVs) that can interconnect multiple layers of 2D silicon photonic electronic integrated circuits consistently with the industry's through-silicon-via (TSV) based 3D electronic integrated circuit manufacturing. Heterogeneous integration technology based on transfer printing allows wafer-scale (or beyond wafer-scale) heterogeneous integration of dissimilar materials (e.g., III-V semiconductor layers) on silicon at room temperature and 3D ultrafast laser inscription technologies allow arbitrary optical interfaces for high-density input/output between the 3D EPICs and many strands of multi-core-fibers (MCFs). We will discuss applications in neuromorphic computing, 3D LiDAR, photonic-integrated-interferometric-telescopes, 3D-fine-grain-memory, and 3D processor-memory realized by large-scale 3D EPICs.

Recent advances in AI bring great challenges on the computing hardware. Memristor based neuromorphic computing can improve the computing density and energy efficiency significantly. However, how to integrate memristive materials and design mixed circuit with advanced CMOS platform is a key challenge. In this presentation, I will talk about our recent progress on heterogeneous integration of memristor and MOSFET. Million-level one-transistor-one-resistor (1T1R) cells can be integrated on a chip. Then I will discuss the co-design technology for memristor/MOSFET mixed circuits. A general purpose neuromorphic computing chip was designed and fabricated to process deep neural networks. I will also introduce our new hybrid training method for eliminating the accuracy loss caused by device variations.