Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect

Abstract

Application-specific Network-on-Chip (ASNoC) has been proposed as a promising solution to address the global communication challenges in System-on-Chips. However, with the number of cores increasing, the on-chip communication becomes more and more complex and the power consumption imposes the major challenge for designing ASNoCs. In this article, we propose a four-stage floorplanning and topology synthesis approach for ASNoCs with Radio-Frequency Interconnect (RF-I). First, considering the advantage of RF-I in long-distance on-chip communication, we integrate the floorplanning and clustering to explore the proper clustering of cores, where the cores belonging to the same cluster will share the same switch for communications, form an island, and occupy a contiguous physical region. After the switches and network interfaces are inserted into the floorplan, the allocation of routing paths and the RF-I logical channels are integrated in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Finally, considering the signal integrity of RF-I, we adjust the placement of the switches by a simulated annealing-based method to reduce the number of RF-I routing corners. To evaluate the placement of switches, we propose a dynamical programming-based method to route the transmission line with the minimized number of routing corners in linear time. The results show that, using the RF-I, we can reduce the power consumption of ASNoCs by 20% to 26%.