Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example

Abstract

Due to their computational complexity, iterative decoder components such as source and channel decoders are usually implemented using specialised dedicated hardware. This leads to the scenario where each different iterative decoder component of the receiver requires its own hardware. Due to their relatively high complexity, many capacity-approaching techniques proposed in the literature have not yet been invoked in wireless sensor network applications, despite their potential benefits of facilitating a reduced transmission power or extended communication range. Against this background, the authors propose an energy-efficient architecture comprised of multiple computation unit (CU), which is sufficiently flexible for accommodating different iterative decoder components using the same hardware. In this study, the flexible architecture is applied to Joint Source and Channel Coding (JSCC), comprising the Unary Error Correction (UEC) code, a turbo code and an iterative demodulator. The authors conceive a flexible technique for controlling the hardware, which supports a high hardware-exploitation ratio for the CU, reaching a utilisation of 88%, compared with 68% achieved in similar solutions reported in the open literature.