FinFET-based fully differential Butterworth filter using a multiple-input dynamic threshold OTA for low-power biomedical signal processing

Low power wireless sensor networks provide a new monitoring and control capability for civil and military applications in transportation, manufacturing, biomedical technology, environmental management, and safety and security systems. Low power integrated CMOS systems are being developed for microsensors, signal processors, microcontrollers, communication transceivers and network access control. This paper covers recent advances in CMOS-based microsensor systems, low power signal processing and RF communication circuits. Communication circuits include the demonstration of a 20 /spl mu/A supply current, 860 MHz, low phase noise CMOS local oscillator.

Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level.

A Novel Carbon Nanotube Field Effect Transistor based Arithmetic Computing Circuit for Low-power Analog Signal Processing Application

In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.

Power and energy minimization has become a significant design requirement for many electronic systems nowadays. As a commonly used arithmetic unit, approximate multiplier is a desirable target for high-speed and low-power digital signal processing. This paper proposes a novel design based on radix-4 partial product generation method, which reduces the height of partial product to half. A new 4-2 compressor is also proposed under the consideration of hardware and accuracy performance for partial product accumulation. As a result, the proposed design for 8-bit multiplication achieves a reduction of power, area and delay up to 49.4%, 53.4% and 48.2% compared to the conventional accurate multiplier. Meanwhile, the accuracy and hardware performance of the proposed design are also compared with several previous works and shows its effectiveness. In addition, the proposed multiplier is also applied to image processing applications without compromising the overall image quality while the power consumption is dramatically reduced.

A monolithic low-power micro-sensor signal processing system with 8bit resolution for the active flow control of micro air vehicles (MAVs) boundary layer separation is proposed, which is composed of an analog low-pass filter, a sigma-delta modulator and a bandgap reference. In order to obtain lower-power, higher-precision and efficient-area, the correlated double sampling (CDS) technology, sub-threshold technology, optimization switches and simple circuit topologies are employed in the design. The overall system was implemented in Central Semiconductor Manufacturing Corporation (CSMC) double-poly three-metal (2P3M) 0.5um 3.3V CMOS technology. The measurement shows that the chip achieves a 54.40dB signal noise ratio (SNR). The die area occupies 3.30mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates only 9.55mW power.

Low-power analogue-sampled-data (ASD) signal processing has traditionally relied on the well-known switched capacitor (SC) technique for the implementation of medical implants, hearing instruments and/or interfaces for battery operated instrumentation. In this paper recent advances in the rapidly maturing switched-current (SI) technique are reviewed with respect to their feasibility for application in novel circuit structures that set the foundations of low-power SI for biomedical signal processing (BSP) and other applications. A qualitative comparison is made between class A and AB SI cells and the mode of MOS transistor operation. The authors briefly discuss building blocks for novel continuously tuneable filtering structures that rely on transconductance-ratios rather than capacitor ratios. Biologically inspired implementations of the cochlea illustrate possible applications. >

Low-power sensors and their applications in various fields ranging from military to civilian lives have made tremendous progress in the recent years. Low-power and extended battery life are the key focuses for long term, reliable and easy operation of these sensors. Sensors and Low Power Signal Processing provides a general overview of a sensors working principle and a discussion of the emerging sensor technologies including chemical, electro-chemical and MEMS based sensors. Also included is a discussion on design challenges associated with low-power analog circuits and the schemes to overcome them. Finally, a short discussion of some of the simple wireless telemetry schemes best suited for low-power sensor applications and sensor packaging issues is discussed. Applications and sensor prototypes included are environmental monitoring, health care monitoring and issues related to the development of sensor prototypes and associated electronics to achieve high signal-to-noise ratio will also be presented.

Connected personal healthcare, or Telehealth, requires smart, miniature wearable devices that can collect and analyze physiological and environmental parameters during a user's daily routine. To truly support emerging applications (Fig. 18.3.1), a generic platform is needed that can acquire a multitude of sensor modalities and has generic energy-efficient signal processing capabilities. SoC technology gives significant advantages for miniaturization. But meeting low-power, medical grade signal quality, multi-sensor support and generic signal processing is still a challenge. For instance, [1] demonstrated a multi-sensor interface but it lacks support for efficient on-chip signal processing and doesn't have a high performance AFE. [2] showed a very low power signal processor but without support for multi-sensor interfacing. [3] presented a highly integrated SoC but lacking power efficiency. This paper demonstrates a highly integrated low-power SoC with enough flexibility to support many emerging applications. A wide range of sensor modalities are supported including 3-lead ECG and bio-impedance via high-performance and low-power AFE. The ARM Cortex™ M0 processor and matrix-multiply-accumulate accelerator can execute numerous biomedical signal processing algorithms (e.g. Independent Component Analysis (ICA), Principal Component Analysis (PCA,) CWT, feature extraction/classification, etc.) in an energy efficient way without sacrificing flexibility. The diversity in supported modalities and the generic processing capabilities, all provided in a single-chip low-power solution, make the proposed SoC a key enabler for emerging personal health applications (Fig. 18.3.1).

Wireless Integrated Network Sensors (WINS) now provide a new monitoring and control capability for transportation, manufacturing, health care, environmental monitoring, and safety and security. WINS combine sensing, signal processing, decision capability, and wireless networking capability in a compact, low power system. WINS systems combine microsensor technology with low power sensor interface, signal processing, and RF communication circuits. The need for low cost presents engineering challenges for implementation of these systems in conventional digital CMOS technology. This paper describes micropower data converter, digital signal processing systems, and weak inversion CMOS RF circuits. The digital signal processing system relies on a continuously operating spectrum analyzer. Finally, the weak inversion CMOS RF systems are designed to exploit the properties of high-Q inductors to enable low power operation. This paper reviews system architecture and low power circuits for WINS.

ABSTRACTPower dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.

Structural health monitoring systems are increasingly used for comprehensive fatigue tests and surveillance of large scale structures. In this paper we describe the development and validation of a wireless system for SHM application based on Lamb-waves. The system is based on a wireless sensor network and focuses especially on low power measurement, signal processing and communication. The sensor nodes were realized by compact, sensor near signal processing structures containing components for analog preprocessing of acoustic signals, their digitization and network communication. The core component is a digital microprocessor ARM Cortex-M3 von STMicroelectronics, which performs the basic algorithms necessary for data acquisition synchronization and filtering. The system provides network discovery and multi-hop and self-healing mechanisms. If the distance between two communicating devices is too big for direct radio transmission, packets are routed over intermediate devices automatically. The system represents a low-power and low-cost active structural health monitoring solution. As a first application, the system was installed on a CFRP structure.

A novel VLSI SOC signal processing circuit technique based on algorithmic computing architecture, ratio based circuit structures and replica (symmetrical) layout implementation employing basic mixed domain VLSI signal processing circuit elements, across the analog, digital, passive, voltage and current circuit domains, is presented. This approach demonstrated high performance, low power, low layout area penalty and low PVT sensitivity for VLSI SOC signal processing circuit implementations. Design examples are also provided in this paper.

Arithmetic digital processing sub-systems are considered as one of the major component of any electronic computing system. The adder/subtractor circuit is one of the vital part of computing systems such as arithmetic logic unit of any computer. Moreover, urge of efficient low loss processing devices are the basic need of the time. This need is the basic motivation for researchers to progress in the field of reversible circuit design approach. Low power VLSI circuits, DNA computing, optical computing, signal processing, quantum computing and nanotechnology etc. are some of the progressive fields with the application of the reversible logic concepts. In this paper, we have proposed an approach to design n-bit adder/subtractor circuits with available reversible logic gates only. The proposed design is compared with existing designs based on some selected factors such as total number of reversible gates used in the design, garbage outputs generated and quantum cost of the design. Based on the proposed design approach, 8-bit adder-subtractor circuit using reversible approach is simulated and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. Application of this optimized circuit may be visualized for the designing of low power processing devices.

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