Abstract
This paper presents a new version of the dynamic SMP cluster -based architecture oriented towards networks on chip implementation technique. Smaller sub-networks with many dynamic SMP clusters and communication on the fly are connected by a central global network. Processors are provided with multi-ported data caches that enable parallel data transactions with memory modules, including parallel data pre-fetching and communication on the fly. Simulation experiments are described, based on a graph program representation and an automatic graph evaluator. They show efficiency of the proposed solution for very fine grain numerical problems.
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