Abstract
The paper answers an open question in the design of complimentary metal-oxide semiconductor (CMOS) VLSI circuits. It asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding /spl epsiv/ such that /spl epsiv/ has a Euler trail P=e/sub 1/e/sub 2/...e/sub m/ and its dual graph has a Euler trail P*=e/sub 1/*e/sub 2/*...e/sub m/* where e/sub i/* is the dual edge of e/sub i/ for i=1, 2, ..., m. The paper answers this question in the affirmative by presenting a linear-time algorithm.
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