Abstract
Second level interconnect (SLI) or board level reliability (BLR) solder joint fatigue has been investigated extensively by OEM, ODM and OSAT. The influencing factors are well understood that package form factor (FF) and BGA pattern are primary factors. Modeling and testing correlate well in identifying failure location and predicting fatigue life. Previously bump level (FLI) is less touched due to large pitch and less fatigue reliability concerns. With the technology shift to more Chip Scale Package (CSP) FF and finer bump pitch, bump fatigue failure frequently occurs and meeting the reliability requirement become more challenging. However, even bump fatigue becomes more prominent, still not enough effort has been invested due to the modeling complexity when UF is present. As the first step towards developing bump fatigue life prediction, we carried out parametric finite element analysis (FEA) and investigated the factors from material, packaging design aspects that are often neglected in BLR. FEA study showed that with the presence of underfill, more factors than SLI/BLR influence the bump fatigue failure prediction. Key parameters that could affect failure location and life prediction are presented here.
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