Fault Mitigation in Reconfigurable NoC Routers with Thin Design Rules

Abstract

Modern networks-on-chip (NoC) for embedded systems are manufactured by thin design rules; they should be resistant to failures due to the specific aspects of the technology. In the paper we consider failure mitigation approaches, evaluate them for thin design rules. Most fault mitigation approaches are based on reconfiguration of NoC and its main components – routers. We suggest the methodology for development of reconfigurable routers with fault mitigation, estimate them using simulation that enables dynamic failure injection. The proposed method can be used for routers with different structures in NoC with various interconnection graphs.