Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field

Abstract

In the modern very large scale integration systems that demand high reliability, a carefully designed power/ground network is essential in order to provide stable power supply to the internal circuits. Although the power supply connection is always checked before tapeout, after the chip fabrication it is quite difficult to evaluate its actual quality and reliability. This paper proposes a novel way to evaluate the on-chip power supply network based on the current estimation using magnetic field emitted from LSI. The proposed method estimates the actual current flow in the network from the magnetic field measurement results and enables us to find defects or design faults such as VIA/wire disconnections and/or current concentration with noninvasive and low-cost way. Experimental results using an electromagnetic field simulator demonstrate that the proposed method precisely estimates the current flow in the supply network. The feasibility of the proposed method is also verified through the actual measurement results of the test structure, which is designed and fabricated in a 0.18- $\mu \text{m}$ 1P5M CMOS process. Near-field magnetic field measurement of the chip was achieved by our high-precision magnetic sensing system and the VIA fault locations on the power supply network were clearly detected by the proposed method.