Failure analysis of EOS-induced damage at final electrical testing

Abstract

The performance and productivity of microelectronics has increased continuously over more than four decades due to enormous advances in photolithography, wafer size, process technology, and devices. Historically, electrical overstress (EOS) has been one of the leading causes of integrated circuit failures. In this paper, the failure sites are observed on an antiparallel diode string within a power cut cell of a 130 nm complementary metal oxide semiconductor mix-signal chip during testing. It was found that the diode string was driven with a forward biased pulse during the power-up and power-down conditions. The slow rise time of the energy pulse indicates that the electrical failure is associated with an EOS event. Failures are verified using scanning electronic microscopy, photoemission microscopy, and liquid crystal analysis. The cause of the failure is either the supply voltage or a timing error in the final testing of the devices.