Abstract

A semiconductor test socket is one of the essential components for final electrical and performance testing of semiconductors. Due to the miniaturization of semiconductors, fine pinching of test sockets is required, so research on connectors for semiconductor inspection capable of fine processing is being actively conducted. The connector for semiconductor inspection consists of a powder coated with conductive powder on a magnetic material and rubber, and an electrical signal is transmitted through the conductive powder. A finer pitch rubber test socket shall maintain the electrical characteristics (resistance) at the same level, even though a smaller conductive path is formed as the gap between conductive paths narrows to respond to the increase in demand for fine pitch products.Therefore, in this study, a technique for forming a conductive pathway between conductive powders to maintain the electrical properties of a semiconductor socket for fine pitch is introduced. In order to effectively improve a thin conductive path, a conductive nanowire was prepared to form a conductive pathway between conductive powders. Fig. 1 shows the schematic diagram for the fabrication of FeCo nanowires. FeCo nanowires were synthesized through electroplating using AAO (Anodic Aluminum Oxide) as a template, and Au as a conductive material was coated on the surface of FeCo wires through an electrochemical method to synthesize FeCo@Au. To uniformly coat Au on the surface of the FeCo wire during the coating process, sonication, vortex, and stay three methods were compared, as shown in Fig. 2. As a result of confirming the surface shape by SEM, the most uniform method was confirmed by the vortex method. In addition, the magnetic properties of FeCo@Au synthesized with a smooth surface were analyzed through VMS (Vibrating Sample Magnetometer). As a result, it can be confirmed that alignment through magnetism is possible. From these results, it was confirmed that the method of increasing the electrical conductivity by adding a wire to reduce resistance of semiconductor connector. Figure 1

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.