Extraction of two-dimensional metal–oxide–semiconductor field effect transistor structural information from electrical characteristics

Abstract

As metal–oxide–semiconductor technology continues to scale to deep submicron feature sizes, the two-dimensional nature of the implanted impurity profiles becomes a critical component of the device design. Device performance in both the off state and on state, as well as device manufacturability, yield, and reliability, depend heavily on a good understanding of the depth, spread, and shape of these profiles. It is often necessary for the device designer to obtain quick, accurate information about these junctions based upon test structures and metal–oxide–semiconductor field effect transistor (MOSFET) electrical characteristics. With junction depths required well below 100 nm for source/drain and lightly doped drain features of very deep submicron MOSFETs, characterization with spatial resolutions on the order of 10 nm is required. In this work, a summary of the techniques used for extracting lateral profile information in a MOSFET channel are presented and compared with physical measurements from the literature. A technique is reviewed which allows extraction of lateral source/drain profile information from the electrical characteristics of a single transistor nondestructively.