Abstract
We have experimentally studied the electron velocity overshoot and the mechanism of its degradation in the inversion layer of sub-0.1 μm metal–oxide–silicon (MOS) field-effect transistors. Both silicon-on-insulator (SOI) and bulk structures were studied. At low transverse electric fields, that is, for low carrier densities in SOI devices under low gate drive conditions, it is possible to achieve electron velocity overshoot due to nonstationary transport in the sub-0.1 μm region. However, it is very difficult in MOS structures to improve electron velocity at high surface electron densities because of the reduced electron mobility in high transverse fields. Moreover, the surface electron density of MOS structures is reduced when a low channel impurity concentration is chosen to improve low field mobility; this results from the expanded inversion layer width. These results indicate the physical limitations of scaled MOS structures with regards to the realization of higher current capabilities.
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