Experimental Investigation of Pattern Layout Effect on Radio-Frequency Performance of Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract

This paper describes design considerations for the thin-film silicon-on-insulator power metal–oxide–semiconductor field-effect transistors for linear-amplification applications. The linear-amplification characteristics and DC performance depend on the grand interconnection pattern. We prefer to put the grand pattern on the drain (output) side. There are optimum finger lengths that provide the best linear amplification characteristics. The finger length also depends on the operating frequency and total gate width.