Abstract
The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted and construction metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. With the consideration of the data consistency and to create a unified method to serve as an industry standard we evaluated 3 approaches: equation based, polygon based, measurement based – to calculate / combine / measure the device EPE. Results will be discussed in the presentation
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