Abstract
Reliability is rapidly emerging as a major design metric in both embedded and high performance computing (HPC) domains. Such systems are integrating modern multicore processors (e.g. big.LITTLE) and graphics processing unit (GPUs) aiming to perform complex software stacks (i.e. operating system OS, drivers, and applications). To ensure failsafe functionality of underlying systems, designers should be able to identify soft errors at the initial design cycle considering different system configurations. In this context, virtual platforms (VPs) appear as an effective means for early design-time assessment of multicore-based systems with respect to soft error resilience. This paper discusses the benefits of using virtual platforms to assess soft errors of multicore-based systems as well as investigates the soft error analysis consistency of an instruction accurate simulator (OVPsim) with respect to a cycle accurate full system simulator (gem5). Fault injection campaigns (more than 1 million) were performed on a multicore ARM processor, considering a Linux Kernel and benchmarks with up to 220 million of object code instructions.
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