Abstract
The interaction of radiation with three-dimensional (3D) electronic devices can be determined through the detection of single-event effects (SEU). In this study, we propose a method for the evaluation of SEUs in 3D static random-access memories (SRAMs) induced by heavy-ion irradiation. The cross-sections (CSs) of different tiers, as a function of the linear energy transfer (LET) under high, medium, and low energy heavy-ion irradiation, were obtained through Monte Carlo simulations. The simulation results revealed that the maximum value of the CS was obtained under the medium-energy heavy-ion penetration, and the effect of penetration range of heavy ions was observed in different tiers of 3D-stacked devices. The underlying physical mechanisms of charge collection under different heavy-ion energies were discussed. Thereafter, we proposed an equation of the critical heavy-ion range that can be used to obtain the worst CS curve was proposed. Considering both the LET spectra and flux of galactic cosmic ray (GCR) and the variation in the heavy-ion Bragg peak values with the atomic number, we proposed a heavy-ion irradiation test guidance for 3D-stacked devices. In addition, the effectiveness of this method was verified through simulations of the three-tier vertically stacked SRAM and the ultrahigh-energy heavy-ion irradiation experiment of the two-tier vertically stacked SRAM. this study provides a theoretical framework for the detection of SEUs induced by heavy-ion irradiation in 3D-integrated devices.
Highlights
As gate-length scaling pushes the development of high-density integrated circuits (ICs) from large-scale integrations to ultra-large-scale integrations, various concerns such as high off-state and sub-threshold leakage, along with substantial delays in wiring, are becoming more serious
For the ground-level heavy-ion radiation testing, the worst experimental conditions should be used to obtain the most conservative radiation results, such that we can screen out the maximum used to obtain the most conservative radiation results, such that we can screen out the maximum safety margin electronic devices
A Monte Carlo simulation was performed to study the discrepancy between the three tiers of SEU CS of three tiers for three types of stacked hypothetical static random-access memories (SRAMs) under high, medium, and low SEU CS of three tiers for three types of stacked hypothetical SRAMs under high, medium, and low incident heavy-ion energies
Summary
As gate-length scaling pushes the development of high-density integrated circuits (ICs) from large-scale integrations to ultra-large-scale integrations, various concerns such as high off-state and sub-threshold leakage, along with substantial delays in wiring, are becoming more serious. It is difficult to obtain high performance through improved integration by scaling the feature size of a transistor. To increase both performance and functionality of ICs and to reduce power and cost, three-dimensional (3D) IC packaging technology emerged as a potential solution [1,2,3]. This 3D IC integration allows multiple two-dimensional (2D) circuits to be stacked vertically as a single die, with improved integration density, noise immunity, superior performance, and higher reliability. Scientists conducted a series of studies on the impact of Electronics 2020, 9, 1230; doi:10.3390/electronics9081230 www.mdpi.com/journal/electronics
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