Evaluate the impact of advanced cell pitch on U-MOSFET wafer edge IGSS failure in a CMOS environment

Critical dimension (CD) bias between a critical dimension scanning electron microscope (CD-SEM) and a reference tool is the most important error factor for more accurate CD measurement. The systematic measurement uncertainty was evaluated by experiment and electron beam simulation. The CD bias variation is caused by the change in secondary electron signal intensity. CD bias variation of an isolated 150 nm silicon substrate space pattern with space width change is 1.7 nm per 10 nm space width. The CD bias difference of the silicon substrate between with and without the native oxide layer is 30 nm at 150 nm space width. The CD bias change is 1.4 nm per 10 nm pattern height. This is caused by an interaction between space width and pattern height. We identified that measurement uncertainty includes not only random error but also systematic error in actual pattern shape, material, and layout variation quantitatively. The impact of systematic error on CD bias is very large compared with the metrology requirement for next-generation devices.

We succeeded in developing the advanced process control (APC) algorithm in gate etching for high mix product line. The gate length is controlled by adjusting the critical dimension (CD) bias based on the optimal etching condition calculated by APC. The CD bias depends on the device pattern as well as the etching condition. Therefore, it is necessary to compensate for the CD bias according to the device pattern in the mix product line. Our APC algorithm enables to adjust the CD bias offset for high mix products automatically. The APC was applied to the sub-micron gate etching of 300-mm wafers. As a result, the gate lengths among the mix products approached to the targets using APC. This demonstrates that our APC algorithm is effective for the high mix product line.

Technology computer-aided design (TCAD) simulation has incessantly solved many complex problems, but it becomes demanding that alternatives be found because TCAD simulation cannot provide precise and fast prediction in the nano-scale era. With the success story of deep learning in research area, many big data companies have attempted to introduce deep learning to support or replace TCAD simulation. The reason is deep learning models have great potential that solves the problems of the TCAD simulation in terms of execution time and coverage. This paper aims to describe various scenarios of deep learning applicable to TCAD. We first describe an application that supplies TCAD data to the deep learning model although TCAD simulation is not calibrated. We then review various approaches that mimic TCAD simulation itself. We finally introduce an application that deep learning model automatically calibrates TCAD models to the measurement without experts. In each scenario, we review the related papers and compare pros and cons.

Reactive ion etching (RIE) and inductively coupled plasma (ICP) Cr etch processes have been evaluated for fabrication of extreme ultraviolet lithography masks on 200 mm substrates. Experiments were completed to optimize the Cr etch rate, etch rate uniformity, and Cr to resist selectivity for both etch processes. The best ICP process was found to have superior etch rate, etch rate uniformity, and comparable Cr to resist selectivity to the RIE process. The effect of exposed Cr area on the Cr to resist selectivity, critical dimension (CD) bias, and CD bias 3σ was also investigated. A decrease in exposed Cr area from 95% to 7% was found to dramatically increase the Cr etch rate, leading to an increase in the Cr to resist selectivity. Lower Cr loading was also found to decrease the CD bias and CD bias 3σ. The average CD bias was very high for both processes, with the ICP etch process having a higher CD bias (143 nm) than the RIE process (89 nm). The CD bias uniformity was significantly lower for the ICP process (32 nm, 3σ) when compared to the RIE process (71 nm, 3σ).

In this paper, we suggest an optimal attenuated phase shift mask (PSM) structure for extreme ultra violet lithography (EUVL) to minimize mask shadowing effect without loss of image contrast. The attenuated PSM proposed in this study is based on Fabry-Perot structure that consists of tantalum nitride (TaN) attenuator, Al₂O₃ spacer, and molybdenum (Mo) phase shifter. Deep ultra violet (DUV) reflectivity can be lowered down to 5% at 257nm for higher efficiency in DUV inspection process through the optimal thickness combination of TaN and Al₂O₃. Since the thickness variation of Mo dose not affect the DUV reflectivity, the phase shift effect can be controlled by Mo thickness only. As a result, attenuated PSM with phase shift of 180±6° and absorber reflectivity of 9.5% could be obtained. The total thickness of absorber stack is only 52nm. The analysis of aerial image was performed using SOLID-EUV simulation tool. The attenuated PSM showed steeper edge profile and higher image contrast compared to binary mask. Imaging properties including horizontal-vertical (H-V) critical dimension (CD) bias and pattern shift depending on both pattern size and process condition were compared to the binary mask using aerial image simulation. Attenuated PSM showed less H-V CD bias compared to that of binary mask. The 32nm dense pattern shows larger H-V CD bias than 45nm one due to larger shadowing of smaller pattern size. Especially, 32nm dense pattern at binary mask has very large H-V CD bias. The H-V CD bias was also affected by the change of focus. However, the H-V bias variation with defocus was below 1nm within the process latitude. We also obtained the result that the pattern shift is less sensitive than H-V CD bias with the optical property of absorber in EUVL.

The purpose of this study is to reduce the critical-dimension (CD) bias (i.e., the difference between actual and measured CD values) for very small line patterns with line widths smaller than 15 nm. The model-based library (MBL) matching technique, which estimates the dimensions and shape of a target pattern by comparing a measured SEM image waveform with a library of simulated waveforms, was modified in two ways to enable it to accurately measure very small patterns. The first modification was the introduction of line-width variation into the library to overcome problems caused by significant changes in waveform due to changes in both sidewall shape and line width. This modification improved the measurement accuracy. The second modification was the fixation of MBL tool parameters that relate to signal-intensity conversion to overcome problems caused by the reduction in pattern shape information due to merging of right and left white bands. This modification reduced the solution space and improved the measurement stability. We confirmed the effectiveness of the modification by using simulated images. We then verified the effectiveness of the modified MBL matching by applying it to actual SEM images. Silicon line patterns with line widths in the range 10-30 nm were used in this experiment, and the CD bias was evaluated by one-to-one comparison with atomic force microscopy (AFM) measurements. The CD bias measured by MBL matching for three heights (20, 50, and 80%) was consistent with the AFM results. The CD biases at all heights were smaller than 0.5 nm and the slopes of the CD biases with respect to the CD were smaller than 3%.

This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to reduce both wafer-to-wafer variation and mask-to-mask variation is developed with the knowledge of peripheral length effect. This technology can also reduce CD variation within die and the CD bias between dense and isolated lines is compensated by optical proximity correction rules. This novel feed-forward technology is one solution for improving every gate CD variation: within die, within wafer, wafer-to-wafer, and mask-to-mask.

Immersion lithography has been developed with great speed. This technology moved to volume production of memory devices about 7 years ago. As immersion lithography developed, various and unexpected problems occurred under 30nm devices. In the act of investigating these problems, it was discovered correlation between Critical Dimension (CD) bias and full-width-at-half-maximum (FWHM). The relationship between wavelength and focus are well known issue [Fig. 1]. Also deviation of wavelength was become a crucial factor on CD bias. These similar phenomena will be frequently happened despite meeting the specification. Therefore this correlation will be able to be a solution for the similar cases.CD bias issue was occurred in 2x nm node production. This phenomenon was expected an aberration problem, presented equation like below. For improving CD bias, chromatic distortion (aberration) had to be minimized by reducing (λ-λo). (λ-λo) is a kind of bandwidth. Also it is called a FWHM. Correlation between aberration and laser wavelength δx(x) = (λ-λo) x dSx/dλ + (λ-λo) x3 dE/dλ where, [δx(x) : chromatic distortion] [(λ-λo) : laser wavelength deviation] [dSx/dλ, dE/dλ : distortion coefficient][x : slit position]The test of narrowing FWHM is done successfully from 0.3pm to 0.25 pm [Fig. 2]. As a result it is obtained better aberration values (coma Z7_0 0.7 nm à 0.4 nm). and CD bias issue was under controlled by E95 (FWHM). Although It is impossible for revealing the exact information about CD in this paper, this problem still occurred similar phenomena. CD bias issue was not easy to solve, However equation and simulations [Fig. 3, Fig. 4] could be explained clearly. Wavelength deviation caused best focus shift, which led to CD bias issue.

Our purpose is to reduce the critical dimension (CD) bias for very small patterns with line widths of <15 nm. The model-based library (MBL) method, which estimates the dimensions and shape of a target pattern by comparing a measured scanning electron microscopy image waveform with a library of simulated waveforms, was modified in two ways. The first modification was the introduction of line-width variation into the library to overcome problems caused by significant changes in waveform due to changes in both sidewall shape and line width. The second modification was the fixation of MBL tool parameters to overcome problems caused by the reduction in pattern shape information due to merging of right and left white bands. We verified the effectiveness of the modified MBL method by applying it to actual silicon patterns with line widths in the range 10-30 nm. The CD bias measured by MBL method for three heights (20, 50, and 80%) was consistent with the atomic force microscopy results. The CD biases at all heights were <0.5 nm, and the slopes of the CD biases with respect to the CD were <3%.

As the technology shrink to smaller Critical Dimension (CD) geometry, Spin On Glass (SOG) and Chemical Mechanical Polishing (CMP) techniques are employed. For 0.30/0.35micrometers processes that uses these techniques, wafer edge dies were having zero yield. These zero yielding wafer edge dies were found to be caused by topography difference between wafer edge and center due to coating, etching and polishing non-uniformity. The use of Wafer Edge Exposure (WEE) using ultraviolet light to create the Edge Bead Removal (EBR) on selected layers provide a more consistent and sharper EBR ring as compared to liquid EBR. This will also result in more complete dies at the wafer edge. The stepper is only able to provide either or no leveling information for the partial wafer edge fields due to the location of the field being too close to wafer edge. In this paper, we present an approach to resolve this problem which addresses the shortcomings of the stepper. We employ a manual top down CD Sem measurements on these non yielding wafer edge dies to check on the CD and profile, a different exposure and/or focus is/are than applied to these non yielding wafer edge field. KLA scan and sort yield are than used to confirm the effectiveness of the changes.

Optical proximity correction (OPC) plays a vital role in the lithography process for critical dimension (CD) control. With the shrinking of the design rule, CD is more sensitive to lithography process, so the task for OPC becomes more challenging. Flare, or stray light, is an added incoherent background intensity that will detract from lithography system performance, CD control and process latitude. The impact of flare on lithographic imaging and its correction through OPC has been the subject of increased investigation. In this paper, the flare effects on CD variation by changing the total image intensity are discussed. The flare map is obtained by running the flare model on the mask layout. Based on the flare map, flare test patterns are designed and flare test reticle is written. After collecting wafer silicon data with CD SEM, flare model is verified and the flare impacts on the across chip line width variation (ACLV) are presented. With the existence of flare, CD bias across different areas of the cell could be measured. As CD varies by a comparatively wider range than optical proximity range, it could not be corrected by existing OPC model. Based on the analysis of flare model and the experiment results, applications on flare correction are discussed by using OPC.

Electrical critical dimension (CD) measurements are now widely used as a characterization technique in optical lithography. In this paper this technique is applied to the determination of the CD and proximity bias variations across the lens field. A method, based on statistical considerations, is introduced to decorrelate the contribution of the mask to the global Across Field linewidth variation (AFLV). It is shown that the mask CD dispersion has an important contribution in the total CD range observed on the wafer. By using this technique, a lens quality determination has been done and the optical contribution to the field CD dispersion has been determined. Moreover, because it is a fast and accurate technique, we show that electrical linewidth measurements can be used in a lens characterization procedure. Results obtained indicate that the proximity bias dispersion across the lens field is not negligible and the question of a dependent field position correction is raising up.

The measurement of critical dimension (CD) using scanning electron microscopy (SEM) brings the blur of CD measured compared with the absolute CD from optical simulation. Although optical property is dominant in PTD process, the CD bias between measurement and simulation with optical model will disqualify the accuracy of CD prediction, EPE calculation and mask correction in SMO. In this paper, using multiple different 1D patterns with different exposure latitude (EL) could discovery the global bias between simulation with optical model and wafer data measured. Due to the property of photoresist shrinkage and the identical profile of PTD through pitches, this bias works well in 1D patterns and assists in anchor re-matching between wafer data and simulation, which could control dose shift between wafer situation and simulation under 1mJ. This bias is also not relevant to source type and will improve the accuracy of PTD SMO highly without resist model.

High Numerical Aperture (NA) extreme ultraviolet lithography (EUVL) with different reduction is one option for 16 nm node and below. In our work, as NA increases to about 0.45, we discuss the impacts of reduction ratio of 5 or 6 on resist image performance such as Horizontal-Vertical (H-V) critical dimension (CD) bias for various incident angles and CD Uniformity induced by mask CD errors at wafer level. Commercial software PROLITH &trade; and in-house program are adopted in simulation referred above. In conclusion, resist image performance can be improved with the increase of reduction ratio. H-V CD Bias with reduction ratio of 6 is obviously smaller than that with reduction ratio of 5 at maximum incident angle. Additionally, CD Uniformity (nm, 3 sigma) induced by mask CD errors for 5× optics system is larger, which means image quality is worse at 5&times; optics system.

In the photolithographic process, critical dimensions (CD) of exposed features in photoresist need to be controlled to within a specified tolerance related to the nominal feature size. A portion of this tolerance budget is consumed by variations in CD on the photomask. At low k1 factor, a number of parameters in the lithography system impact linearity including lens aberrations, defocus, exposure, partial coherence, and photoresist contrast. The combined effect of these parameters is that errors in the mask CDs are not transferred to the wafer in direct proportion to the optical reduction value of the lithography system. This Mask Error Factor (MEF) becomes a significant problem as it consumes a larger than anticipated portion of the CD tolerance budget. This paper will discuss experimentally evaluated MEF using a 4X i-line stepper for a range of feature sizes from subwavelength to approximately twice the exposure wavelength. A test reticle was built with isolated lines from 200 nm to 600 nm in 12.5 nm increments at 1 X. CD measurements on the reticle were compared to corresponding CD measurements on the wafer in order to establish both linearity and MEF curves for the lithography system. MEF values were also determined across a process window for multiple feature sizes. The MEF was observed to be less than 1.4 for CDs greater than 330 nm (k1 equals 0.5) throughout the process window. However, the MEF rises rapidly to over 3 for CD values smaller than 300 nm (k1 equals 0.45) at nominal focus and exposure. Changes in exposure were not observed to have a noticeable impact on MEF while focus offsets were observed to result in significant increases in MEF. These results indicate that MEF has a much larger impact on focus latitude than on exposure latitude. As a result the process window will be compressed more in focus than in exposure.