Ethanol-assisted direct synthesis of wafer-scale nitrogen-doped graphene for III-nitride epitaxial growth

Wafer-scale monolayer graphene film was synthesized on Cu foils by chemical vapor deposition in a 3-in thermal furnace. Graphene film was transferred to the surface of SiO2 (300 nm)/Si substrates using a polymer-assisted method. Hall bar structures were fabricated by lithography and E-beam deposition for the electrical property measurement. Perfect symmetrical ohmic resistance distribution was achieved. The longitudinal resistance was measured at different temperatures, and it showed negative differential resistance behavior with temperatures below 88K. Wafer scale graphene were also transferred to a flexible poly (ethylene terephthalate) (PET) substrate for flexible electronics application. The transmittance of the monolayer graphene at 550 nm was measured to be 95.6% and the sheet resistance was 5.6kΩ/□.

Graphene has attracted wide interest due to its promising potential applications in electronics and photonics. However, many of these applications are restricted by zero band gap of graphene. Nonetheless, a considerable band gap of up to 250 meV can be opened up in Bernal (AB) stacked bilayer graphene by applying a perpendicular electric field between the two superimposed layers. Hence, graphene synthesis has been focused on growing high-quality and large-area AB-stacked bilayer graphene. Chemical vapour deposition (CVD) is a favourable synthesis technique for graphene since it can grow high-quality and large-area or wafer-scale graphene, which is important for electronic devices. In addition, atmospheric-pressure CVD is technologically more accessible for graphene growth. The metallic substrate like Cu which mostly used for CVD grown graphene is found to be favouring to grow monolayer graphene because of limitation of C arbsorption in Cu, while Cu substrate engineered with Ni is found to grow multilayer graphene because of significant arbsorption of C in Ni and hence if it well controlled it can grow AB stacked graphene. In this study we focuse on the AP-CVD synthesis and characterization of high-quality and wafer-scale (scale of an entire foil) AB-stacked bilayer graphene film obtained on a dilute Cu(0.61 at% Ni) foil and compared the growth to the results of AP-CVD growth under identical conditions on pure Cu foil. Atomic force microscopy (AFM) average step height analysis showed thickness of bilayer graphene, scanning electron microscopy (SEM) micrographs showed uniform and continuous graphene layers and the Raman optical microscopy images and spectroscopy data supported by selected area electron diffraction (SAED) data showed high-quality and continuous (wafer-scale) AB-stacked bilayer graphene for graphene film obtained on a dilute Cu(0.5 at% Ni) foil.

Frank-van der Merwe growth in bilayer graphene

In this research, we constructed a controlled chamber pressure CVD (CP-CVD) system to manipulate graphene's domain sizes and shapes. Using this system, we synthesized large (~4.5 mm(2)) single-crystal hexagonal monolayer graphene domains on commercial polycrystalline Cu foils (99.8% purity), indicating its potential feasibility on a large scale at low cost. The as-synthesized graphene had a mobility of positive charge carriers of ~11,000 cm(2) V(-1) s(-1) on a SiO(2)/Si substrate at room temperature, suggesting its comparable quality to that of exfoliated graphene. The growth mechanism of Cu-based graphene was explored by studying the influence of varied growth parameters on graphene domain sizes. Cu pretreatments, electrochemical polishing, and high-pressure annealing are shown to be critical for suppressing graphene nucleation site density. A pressure of 108 Torr was the optimal chamber pressure for the synthesis of large single-crystal monolayer graphene. The synthesis of one graphene seed was achieved on centimeter-sized Cu foils by optimizing the flow rate ratio of H(2)/CH(4). This work should provide clear guidelines for the large-scale synthesis of wafer-scale single-crystal graphene, which is essential for the optimized graphene device fabrication.

Synthesis of Large-Area Single-Crystal Graphene

Wafer-scale growth of single-crystal graphene on vicinal Ge(001) substrate

Graphene is considered as a material which can enable new functionalities and performance improvements in a large variety of applications, among them in microelectronics [1, 2]. In microelectronics, techniques required for commercial large scale fabrication of graphene devices are not yet in place and further progress towards wafer-scale processing is required. Development of a wafer-scale Si technology-compatible graphene synthesis method and a toolbox of processes dedicated to handling, cleaning, patterning as well as integration of graphene with semiconductors, insulators, and metals is viewed as a prerequisite to practical applications of this material in electronic and photonic devices [3]. Semiconducting Ge surfaces appeared recently as attractive substrates for chemical vapor deposition (CVD) of graphene. There are several advantages of using them instead of metals. Firstly, the risk of metallic contaminations [4] is eliminated, ensuring the front-end-of-line compatibility in the device manufacturing process. Secondly, the thermal expansion coefficient mismatch between the Ge substrate and graphene is significantly lower than in the Cu-graphene system. This provides an opportunity to reduce the density of wrinkles which originate from thermal stress release and cause scattering of charge carriers in graphene. Furthermore, as a result of very low carbon solubility in Ge, the graphene growth on Ge can proceed, similarly to Cu substrates, in a “self-limiting” manner enabling more straightforward process control than for example on Ni. Finally, synthesis on patterned semiconducting Ge may enable direct use of graphene in some device concepts without the need of transfer which is inevitable in case of metallic substrates. In this talk, we will review the recent progress in graphene synthesis on Ge achieved by IHP and our collaborators starting from proof-of-concept molecular beam growth experiments [5], through low- [6] and high-pressure [7] CVD on Ge single crystals and Ge epi-layers on Si, to 200 mm wafer-scale CVD synthesis on Ge(100)/Si(100) virtual substrates. As an optimization approach towards improved rotational alignment of graphene on Ge [8,9] we will present results from the preparation of Ge(110)/Si(110) wafers and graphene growth on them. Beyond growth we will look at selected aspects of subsequent processing in a 200 mm Si wafer pilot line including patterning and interaction with photoresists as well as the deposition of other materials on graphene. Among the challenges ahead, re-usability of the Ge virtual substrates and wafer-scale graphene transfer procedures eliminating disadvantages of currently existing noble metal-assisted techniques [8] will be addressed. [1] A.C. Ferrari et al., “Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems”, Nanoscale, 2015, 7, 4598-4810 [2] G. Fiori et al., “Electronics based on two-dimensional materials”, Nature Nanotechnology 2014, 9, 768–779 [3] L. Colombo et al., “Graphene growth and device integration”, IEEE Proceedings, 2013, 101, 1536-1556 [4] G. Lupina et al., “Residual metallic contamination of transferred chemical vapor deposited graphene”, ACS Nano, 2015, 9, 4776-4785 [5] G. Lippert et al., “Graphene grown on Ge(001) from atomic source”, Carbon, 2014, 75, 104-112 [6] J. Dabrowski et al., “Direct growth of low-doped graphene on Ge/Si(100) surfaces”, 2016, arXiv:1604.02315 [7] I. Pasternak et al., “Graphene growth on Ge(100)/Si(100) substrates by CVD method”, Scientific Reports, 2016, 6, 21773 [8] J.-H. Lee et al., “Wafer scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium”, Science, 2014, 344, 286-289 [9] B. Kiraly et al., “Electronic and mechanical properties of graphene-germanium interfaces grown by chemical vapor deposition”, Nano Lett., 2015, 15, 7414-7420

Graphene is an interesting material because it has remarkable properties, such as high intrinsic carrier mobility, good thermal conductivity, large specific surface area, high transparency, and high Young’s modulus values. It is produced by mechanical and chemical exfoliation, chemical vapor deposition (CVD), and epitaxial growth. In particular, large-area and uniform single- and few-layer growth of graphene is possible using transition metals via a thermal CVD process. In this study, we utilize polystyrene and boron oxide, which are a carbon precursor and a doping source, respectively, for synthesis of pristine graphene and boron doped graphene. We confirm the graphene grown by the polystyrene and the boron oxide by the optical microscope and the Raman spectra. Raman spectra of boron doped graphene is shifted to the right compared with pristine graphene and the crystal quality of boron doped graphene is recovered when the synthesis time is 15 min. Sheet resistance decreases from approximately 2000 Ω/sq to 300Ω/sq with an increasing synthesis time for the boron doped graphene.

One of the main problems in our society is the energy production and storage. Ion-Li batteries are commonly used as an alternative for energy production but have the disadvantages of a poor recharged cycles and the possibility of fire. Researches are done to develop efficient anodes and cathodes for batteries and one of the possible alternatives is the use of graphene. Due to its unique planar structure, transparency, mechanical strength, thermal properties, and electronic conductivity, graphene is a very promising material for nanoelectronic devices, sensors, energy-storage and/or transparent conducting electrodes applications. The exceptional properties of graphene are a consequence of the continuous network of hexagonally arranged sp2-bonded carbon atoms in a 2D-structure. Among the different synthesis processes to obtain graphene (i.e. chemical exfoliation, mechanical cleavage, epitaxial growth or chemical vapor deposition-CVD), the last one (CVD) is considered as the most promising procedure to obtain continuous graphene flakes, with very low level of defects. Although the presence of unwanted byproducts and structural damages is unavoidable, this method is one of the most suitable for large-scale and controllable synthesis of graphene. Commonly, the synthesis of graphene by CVD requires a copper or nickel sheet as substrate, and alcohols or methane as carbon source. In this research, a CVD method, slightly modified with respect to the standard procedure, has been used to obtain graphene flakes (see Figure 1). Thus, a mixture of ethanol:N2:H2 was used to obtain a blue plasma at high temperature, responsible for the synthesis of graphene. A complete analysis of the as-synthesized graphene flakes has been performed using a combination of tools including scanning and transmission electron microscopies (SEM and TEM), Raman spectroscopy, X-ray photoemission spectroscopy (XPS), atomic force microscopy (AFM) and infrared spectroscopy (FT-IR). Figure 1

Growth and characterization of graphene grown using copper foils as well as copper films on silicon dioxide on silicon substrates were performed. Kinetics of growth and effective activation energy for the graphene synthesis will be discussed for the surface catalytic synthesis of graphene. Conditions for large-scale synthesis of monolayer graphene will be addressed in this talk. Wafer-scale graphene transfer and electrical results will be presented. Based on our preliminary results from capped 100mm wafer scale graphene transistors, we expect a mobility of 4-6 k cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs with symmetry hole/electron transport. Key considerations and challenges for scaling are discussed and results for graphene growth on the 300mm wafer scale will be discussed.

A method for the direct synthesis of wafer-scale graphene on dielectric substrates using trace amounts of carbon found in metals is reported. Graphene films were synthesized through a single-step thermal annealing process of a Cu/Ni bilayer deposited on a SiO2/Si and a quartz substrate in a low pressure H2/Ar environment. No additional carbon source was provided. The Cu film partially evaporated during growth, leaving a graphene layer above and beneath the Ni film. A wet etch step allowed complete removal of the metals, resulting in continuous graphene coverage of the surface. A simple pattered synthesis of graphene was performed using this technique demonstrating the ability to control the growth of graphene to specific regions over large areas of the wafer.

Spintronics reaches beyond typical charge-based information storage technologies by utilizing an addressable degree of freedom for electron manipulation, the electron spin polarization. With mounting experimental data and improved theoretical understanding of spin manipulation, spintronics has become a potential alternative to charge-based technologies. However, for a long time, spintronics was not thought to be feasible without the ability to electrostatically control spin conductance at room temperature. Only recently, graphene, a 2D honeycomb crystalline allotrope of carbon only one atom thick, was identified because of its predicted, long spin coherence length and experimentally realized electrostatic gate tunability. However, there exist several challenges with graphene spintronics implementation including weak spin-orbit coupling that provides excellent spin transfer yet prevents charge to spin current conversion, and a conductivity mismatch due to the large difference in carrier density between graphene and a ferromagnet (FM) that must be mitigated by use of a tunnel barrier contact. Additionally, the usage of graphene produced via CVD methods amenable to semiconductor industry in conjunction with graphene spin valve fabrication must be explored in order to promote implementation of graphene-based spintronics. Despite advances in the area of graphene-based spintronics, there is a lack of understanding regarding the coupling of industry-amenable techniques for both graphene synthesis and lateral spin valve fabrication. In order to make any impact on the application of graphene spintronics in industry, it is critical to demonstrate wafer-scale graphene spin devices enabled by wafer-scale graphene synthesis, which utilizes thin film, wafer-supported CVD growth methods. In this work, high-quality graphene was synthesized using a vertical cold-wall furnace and catalyst confinement on both SiO2/Si and C-plane sapphire wafers and the implementation of the as-grown graphene for fabrication of graphene-based non-local spin valves was examined. Optimized CVD graphene was demonstrated to have ID/G ≈ 0.04 and I2D/G ≈ 2.3 across a 2" diameter graphene film with excellent continuity and uniformity. Since high-quality, large-area, and continuous CVD graphene was grown, it enabled the fabrication of large device arrays with 40 individually addressable non-local spin valves exhibiting 83% yield. Using these arrays, the effects of channel width and length, ferromagnetic-tunnel barrier width, tunnel barrier thickness, and level of oxidation for Ti-based tunnel barrier contacts were elucidated. Non-local, in-plane magnetic sweeps resulted in high signal-to-noise ratios with measured ΔRNL across the as-fabricated arrays as high as 12 Ω with channel lengths up to 2 µm. In addition to in-plane magnetic field spin signal values, vertical

The growth of inch-scale high-quality graphene on insulating substrates is desirable for electronic and optoelectronic applications, but remains challenging due to the lack of metal catalysis. Here we demonstrate the wafer-scale synthesis of adlayer-free ultra-flat single-crystal monolayer graphene on sapphire substrates. We converted polycrystalline Cu foil placed on Al2O3(0001) into single-crystal Cu(111) film via annealing, and then achieved epitaxial growth of graphene at the interface between Cu(111) and Al2O3(0001) by multi-cycle plasma etching-assisted-chemical vapour deposition. Immersion in liquid nitrogen followed by rapid heating causes the Cu(111) film to bulge and peel off easily, while the graphene film remains on the sapphire substrate without degradation. Field-effect transistors fabricated on as-grown graphene exhibited good electronic transport properties with high carrier mobilities. This work breaks a bottleneck of synthesizing wafer-scale single-crystal monolayer graphene on insulating substrates and could contribute to next-generation graphene-based nanodevices.

Wafer-scale fabrication of single-crystal graphene on Ge(1 1 0) substrate by optimized CH4/H2 ratio

The synthesis of transfer-free graphene is necessary for expanding its industrial applications. Although the direct synthesis of graphene on the insulating substrate via a metal sacrificial film was reported, the growth mechanism of transfer-free graphene still remains to be studied. Herein, a detailed synthesis model of graphene grown from different carbon sources has been established to help in selecting the growth conditions for high-quality graphene. A detailed discussion on the critical influence of dissolution and the diffusion rate of carbon atoms on the growth process has also been presented. The high decomposition temperature carbon sources promote the formation of high-quality monolayers of graphene. The carbon diffusion rate of the Cu film is significantly higher than that of Ni. This promotes the synthesis of graphene from methane and diamond-like carbon. However, adverse effects are exerted on polymethyl methacrylate. Ion implantation technology and different components of the Ni–Cu alloy were used to understand this growth mechanism. This work could guide the growth conditions of transfer-free, large-scale, and high-quality graphene that can be potentially used for the fabrication of a semiconductor or an insulation substrate in theory. The reported method can generate interest in the field and increase the industrial applications of graphene-based devices that exhibit rough or patterned surfaces.