Abstract
In this work a high-κ-metal-gate patterning-process using ICP-RIE is proposed. The dry-etching is low on plasma-induced damages and highly selective to the dielectric due to its low bias-voltage. A self aligned removal of the high-κ-layer is also applied to complete the gate-stack patterning. This procedure may substitute replacement-gate-processes for high-κ-metal-gate CMOS-transistors.
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