ESD laboratory simulations and signature analysis of a CMOS programmable logic product

Abstract

It is well established in the semiconductor I/C industry that the proportion of customer field returns attributed to damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40% to 50% (Cook C, Daniel S. Characteristics and failure analysis of advanced CMOS submicron ESD protection structures. EOS/ESD symposium proceedings ♯14, Dallas, TX, 1992. p. 147; Denson WK, Green TJ. A review of EOS/ESD field failures in military equipment. EOS/ESO symposium proceedings-10, 1988. p. 7. Straub RJ. Automotive Electronics IC Reliability. CICC Proceedings, 1990; Euzent BL, Maloney TJ, Donner II R. Reducing field failure rate within proven EOS/ESO design. EOS/ESO Symposium Proceedings ♯13, Los Vegas, NV, 1991. p. 59). ESD events are the subset of EOS events caused by high voltages that are associated with electrostatic charge. Although additional hard and soft failures can occur in the factory, these are normally screened by effective test programs. It is therefore necessary to determine the probable cause of failure before cost effective corrective action can be initiated. Distinguishing between EOS and ESD failures and differentiating the subtle differences between damage due to the several distinct ESD models continues to challenge failure analysis capabilities as dimensions shrink and critical defect sizes are reduced. Many of the damage sites are not visible with optical microscopy. De-processing together with very high magnification examination using the scanning electron microscope (SEM) is most often necessary. However, the use of test model simulators to replicate the ESD events can most often replicate a failure signature, i.e. a unique die location and morphology associated with the specific model (Morgan IH. ESO Failure Analysis Signatures. Proceedings of the 3rd ESO Forum, Grain, Germany, 1993. p. 275). This paper summarizes the evaluation performed on a standard programmable logic complimentary metal-oxide silican (CMOS) product to ascertain the ESD immunity. The study entailed ESD simulation using a variety of ESD models, conducting detailed physical failure analysis and then comparing the results with documented analyses performed on customer field returns and factory failures. As a result of the differences in current stress magnitude and over-stress time domain, the location, type and severity of damage at the failure site is known to show considerable variation (Morgan IH. A Handbook of ESO models. AMD Internal Publication, 1992 (available from AMD literature department upon request)). The purpose of the study was to develop a catalogue of failure signatures, and to determine to what extent this catalogue could be used to relate a signature to electrical failure for a particular die and pin function.