Equidistance routing in high-speed VLSI layout design

Abstract

In VLSI system, a certain set of nets is required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. This paper approaches this problem by the concept of l-equidistance routing which aims to route the concerned nets by prescribed length l. After a basic technique to route a 1-sink net with prescribed length, an algorithm is presented for the channel routing where sink terminals are on the upper line and source terminals on the bottom lines. The key idea is in the symmetric slant grid interconnect scheme by which the problem is reduced to the ordinary grid routing problem. An algorithm that attains minimum total wire length is presented. Then a solution is given for the case when terminals are on the perimeters on a rectangle. These algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the orthogonal grid is possible keeping the property of equidistance. Proposed algorithms were implemented and applied to random data to demonstrate their ability.