Enhancing Safety in Aquaculture with Nanostructures: Hazard Detection and Elimination

We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is apparent that the proposed approach can be practiced for every digital circuit with combinational loops. In regard to hazard detection, a simulation-based semi-modular analysis is presented, by extending the provided library technology behavioral Verilog files. For hazard elimination, only the standard cells within the paths causing a hazard have been included for analysis. The circuit becomes hazard-free by inserting buffers of the minimum required delay. We develop three path-based buffer insertion approaches; the more advanced ones model each logic gate and their relative timing constraints as a maximum set covering problem. The main characteristic of comparison is the count of inserted buffers and their total delay. The aforementioned hazard analysis is an iterative process, because the overall timing constraints of the circuit alter after each delay insertion. Experimental results indicate that the three hazard elimination approaches have various area penalties and their success rate ranges from 68.7% to 100%. Moreover, not all hazards can be resolved, mainly due to opposing constraints of sensitized hazard paths, and Boolean logic re-synthesis may be required.

This paper is concerned with the study of static hazards in combinational switching circuits by means of a suitable ternary switching algebra. Techniques for hazard detection and elimination are developed which are analogous to the Huffman-McCluskey procedures. However, gate and series-parallel contact networks are treated by algebraic methods exclusively, whereas a topological approach is applied to non-series-parallel contact networks only. Moreover, the paper derives necessary and sufficient conditions for a ternary function to adequately describe the steady-state and static hazard behavior of a combinational network. The sufficiency of these conditions is proved constructively leading to a method for the synthesis of combinational networks containing static hazards as specified. The section on non-series-parallel contact networks also includes a brief discussion of the applicability of lattice matrix theory to hazard detection. Finally, hazard prevention in contact networks by suitable contact sequencing techniques is discussed and a ternary map method for the synthesis of such networks is explained.

A logic hazard detection and elimination method