Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

Abstract

To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO-based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer (~ 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm2/V s and the Vth uniformity of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured Vth shift of CL-ES-structured device significantly decreased to − 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (− 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor-based process for LCD fabrication is highly feasible.