Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

Abstract

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multiple-output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm 2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 × 4 QR decomposition, 4 × 4 singular value decomposition, and 2 × 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]-[16]. It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform.