Enabling energy-proportional computing on instruction-level parallel processors

Abstract

Digital signal processor (DSP) cores with very-long-instruction-word (VLIW) architectures have been widely used in recent embedded and multimedia systems-on-chips. Improving power efficiency becomes a crucial issue for designing VLIW-DSP cores. This paper proposes a novel approach--energy-proportional parallel computing--to improve the power efficiency of a VLIW-DSP core. The main theme in this approach is to adapt parallelism by performance demand and apply power gating to idle hardware. The challenge is to reduce the power dissipated on register files. Energy proportionality is realized through an architecture featuring distributed and power-gated register files. Power efficiency is exploited by the compiler through instruction scheduling and register allocation. Energy-aware list scheduling is proposed to reduce the register file power, while building an as-soon-as-possible schedule. Following the scheduling outcome, register allocation with energy-oriented decision rules through weighted graph coloring is performed. Evaluation with the MiBench benchmark suite shows a significant power saving and scaling range on the register file power. Moreover, the evaluation justifies the effect of a power-gated processor to maintain good energy efficiency over applications with diverse behavior. This result shows that energy-proportional parallel computing is an attractive direction for future processor design in the deep-submicron era.