Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic

Abstract

A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.