Embedded FeRAM Challenges in the 65-nm Technology Node and Beyond

Abstract

To embedded ferroelectric random access memories in the 65-nm CMOS and beyond, three-dimensional structure and low-temperature formation have been developed. As the semiconductor technology moves toward the 65-and 45-nm nodes, the role of nonvolatile memories embedded in system-on-a-chips (SoCs) is becoming extremely important. Especially in ferroelectrics, bismuth-layered perovskite materials such as SrBi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sub> (SBT) can provide SoCs with fast read/write speed, low-voltage and fatigue-free memory performances. Until now, however, ferroelectric random access memory (FeRAM) technology has been two or three generations behind the leading-edge CMOS. Now therefore, we need adventurous technology transition in FeRAM materials and processing to catch up with the leading-edge CMOS. In this paper, we give overview of the current status of the FeRAM technology. Future challenges facing the FeRAM technology are also described.