Emμcode: Masking hard faults in complex functional units

Abstract

This paper presents Emmucode, a technique for masking hard faults in modern microprocessors that provides graceful performance degradation. Emmucode employs microcode traces with control flow that replace an original instruction once a fault is detected. Emmucode adds lightweight microarchitectural hardware to assist in correcting hard faults in larger structures, such as SIMD execution units found in contemporary microprocessors, where replication is infeasible. Key challenges in implementing microcode traces include maintaining proper architectural state and the optimization of trace code. We are able to significantly optimize traces by exploiting dynamic trace behavior and by performing minor modifications to the microarchitecture. We find that removing hard to predict branches is important for optimizing traces. Emmucode uses partial predication, new microcode operations, and the full use of the microcode's flexibility and visibility to create fast traces. This paper studies the viability of implementing SIMD floating point arithmetic operations found in modern x86 processors using Emmucode traces. Our results show that for programs with 1 to 5 percent of the dynamic instructions replaced by Emmucode, a graceful performance degradation of only 1.3times to 4times is achievable.