Abstract
A GaAs-on-Si technology is desirable to take advantage of the mobility and direct bandgap of GaAs in combination with the crystalline quality, low cost and established technology of Si. Differences in lattice constant (4.1%), thermal expansion coefficient (a factor of ~ 3), and bonding polarity between the two materials can lead to problems such as: threading dislocation formation, thermally induced stress and delamination, and antiphase domain boundaries (APBs), respectively. The lattice mismatch is responsible for the formation of (necessary) misfit dislocations which can concurrently create threading dislocations with typical densities in the range of 106 - 108cm-2. This density of electrically active defects in a device region is highly undesirable.A proposed scheme for lattice mismatch accommodation and potential threading dislocation reduction has previously been reported in which each layer of a SixGe1-x multilayer structure (MLS) is grown beyond the critical thickness with a progressively higher Ge composition than the previous layer.
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