Abstract
A class of VLSI architectures for data transformation of tree-based codes is proposed, concentrating on transformation functions used for data compression and decompression. Two algorithms are presented: a sequential algorithm that generates the code bits serially one bit per machine cycle, and a parallel algorithm that generates the entire code bits of a symbol in one machine cycle. The algorithms use the principle of propagation of a token in a reverse binary tree constructed from the original codes. The design approaches are applicable to any binary codes, although the static Huffman code is used as an illustration. A hardware algorithm for generating adaptive Huffman codes is proposed, and a VLSI architecture for implementing the algorithm is described. The high speed of the algorithms ensures that data transformation is done on the fly, as data are being transferred from/to high-speed I/O communication devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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